Patents by Inventor I-Ming Chang
I-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11018022Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.Type: GrantFiled: July 13, 2018Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Ming Chang, Chih-Cheng Lin, Chi-Ying Wu, Wei-Ming You, Ziwei Fang, Huang-Lin Chao
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Patent number: 10985265Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.Type: GrantFiled: August 22, 2019Date of Patent: April 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Liang Cheng, I-Ming Chang, Hsiang-Pi Chang, Hsueh-Wen Tsau, Ziwei Fang, Huang-Lin Chao
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Patent number: 10978357Abstract: A method for forming a semiconductor arrangement includes forming a fin. A diffusion process is performed to diffuse a first dopant into the channel region of the fin. A first gate electrode is formed over the channel region of the fin after the first dopant is diffused into the channel region of the fin.Type: GrantFiled: June 6, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Ming Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Hsueh Wen Tsau, Ziwei Fang
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Patent number: 10971402Abstract: A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer.Type: GrantFiled: June 17, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Liang Cheng, I-Ming Chang, Hsiang-Pi Chang, Yu-Wei Lu, Ziwei Fang, Huang-Lin Chao
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Publication number: 20210098457Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Liang CHENG, I-Ming CHANG, Ziwei FANG, Huang-Lin CHAO
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Publication number: 20210057550Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Liang CHENG, I-Ming CHANG, Hsiang-Pi CHANG, Hsueh-Wen TSAU, Ziwei FANG, Huang-Lin CHAO
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Patent number: 10915133Abstract: A voltage regulator circuit is presented that can generate a stable and well-regulated output level to supply loads that have large dynamic current and capacitive variation. A compensation circuit is added to introduce a zero that tracks the voltage regulator's non-dominant pole. The compensation circuit includes a compensation transistor, whose gate is connected to receive the same voltage as the regulator's load driving pass transistor, and a series combination of a capacitance and a tracking resistance connected in series between the compensation transistor's gate and a supply level, where the value of the tracking resistance depends on the current supplied to the load. The tracking resistance can be implemented as a diode connected NMOS through which the compensation transistor is connected to the low supply level, or a diode connected PMOS whose current tracks that of the compensation transistor through a current mirror.Type: GrantFiled: February 25, 2020Date of Patent: February 9, 2021Assignee: SanDisk Technologies LLCInventors: Xiaofeng Zhang, Naresh Battula, Albert I-Ming Chang
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Publication number: 20200395250Abstract: A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Inventors: Chung-Liang CHENG, I-Ming CHANG, Hsiang-Pi CHANG, Yu-Wei LU, Ziwei FANG, Huang-Lin CHAO
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Publication number: 20200335608Abstract: A semiconductor includes a substrate, a semiconductor fin, an STI structure, a fin sidewall spacer, and a doped silicon layer. The semiconductor fin extends from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The fin sidewall spacer extends along a middle portion of the semiconductor fin that is above the lower portion of the semiconductor fin. The doped silicon layer wraps around three sides of an upper portion of the semiconductor fin that is above the middle portion of the semiconductor fin.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Sheng HUANG, Hung-Chang SUN, I-Ming CHANG, Zi-Wei FANG
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Publication number: 20200303260Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01?x?0.1, and 0.01?y?0.1.Type: ApplicationFiled: June 9, 2020Publication date: September 24, 2020Inventors: Yasutoshi OKUNO, Cheng-Yi PENG, Ziwei FANG, I-Ming CHANG, Akira MINEJI, Yu-Ming LIN, Meng-Hsuan HSIAO
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Publication number: 20200303259Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0<a, 0<b, 0.01?(a+b)?0.1, 0.01?y?0.1, and M2 is P or As.Type: ApplicationFiled: June 9, 2020Publication date: September 24, 2020Inventors: Yasutoshi OKUNO, Cheng-Yi PENG, Ziwei FANG, I-Ming CHANG, Akira MINEJI, Yu-Ming LIN, Meng-Hsuan HSIAO
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Patent number: 10707333Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.Type: GrantFiled: November 14, 2018Date of Patent: July 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Sheng Huang, Hung-Chang Sun, I-Ming Chang, Zi-Wei Fang
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Patent number: 10685884Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.Type: GrantFiled: July 31, 2017Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yasutoshi Okuno, Cheng-Yi Peng, Ziwei Fang, I-Ming Chang, Akira Mineji, Yu-Ming Lin, Meng-Hsuan Hsiao
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Publication number: 20200176328Abstract: A method for forming a semiconductor arrangement includes forming a fin. A diffusion process is performed to diffuse a first dopant into the channel region of the fin. A first gate electrode is formed over the channel region of the fin after the first dopant is diffused into the channel region of the fin.Type: ApplicationFiled: June 6, 2019Publication date: June 4, 2020Inventors: I-Ming CHANG, Chung-Liang Cheng, Hsiang-Pi Chang, Hsueh Wen Tsau, Ziwei Fang
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Publication number: 20200168507Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.Type: ApplicationFiled: April 2, 2019Publication date: May 28, 2020Inventors: I-MING CHANG, CHUNG-LIANG CHENG, HSIANG-PI CHANG, HUNG-CHANG SUN, YAO-SHENG HUANG, YU-WEI LU, FANG-WEI LEE, ZIWEI FANG, HUANG-LIN CHAO
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Publication number: 20200152746Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.Type: ApplicationFiled: February 15, 2019Publication date: May 14, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Wen TSAU, Chun-I WU, Ziwei FANG, Huang-Lin CHAO, I-Ming CHANG, Chung-Liang CHENG, Chih-Cheng LIN
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Publication number: 20200035811Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.Type: ApplicationFiled: November 14, 2018Publication date: January 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Sheng HUANG, Hung-Chang SUN, I-Ming CHANG, Zi-Wei FANG
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Publication number: 20200020544Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Ming CHANG, Chih-Cheng LIN, Chi-Ying WU, Wei-Ming YOU, Ziwei FANG, Huang-Lin CHAO
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Publication number: 20190035691Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.Type: ApplicationFiled: July 31, 2017Publication date: January 31, 2019Inventors: YASUTOSHI OKUNO, CHENG-YI PENG, ZIWEI FANG, I-MING CHANG, AKIRA MINEJI, YU-MING LIN, MENG-HSUAN HSIAO
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Patent number: 9978630Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.Type: GrantFiled: June 8, 2015Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang