Patents by Inventor Ian A. Young

Ian A. Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312086
    Abstract: An apparatus is provided which comprises: a first magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; a second magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; and a first layer of spin orbit coupling material adjacent to the first magnetic junction and the second magnetic junction via their respective 4-state free magnetic layers. Described is an apparatus which comprises a 4-state free magnetic layer; a layer of SOC material adjacent to the 4-state free magnetic layer; a first interconnect coupled to the layer of SOC material.
    Type: Application
    Filed: December 5, 2016
    Publication date: October 10, 2019
    Applicant: Intel Corporaration
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10439599
    Abstract: Embodiments include circuits, apparatuses, and systems for non-boolean associative processors. In embodiments, an electronic associative processor circuit may include first and second ring oscillators, each having an odd number of inverters, an input terminal, and an output terminal. A first capacitor may have a first terminal coupled with the output terminal of the first ring oscillator and a second capacitor may have a first terminal coupled with the output terminal of the second ring oscillator. Second terminals of the first and second capacitors may be coupled at an oscillator stage output terminal. The inverters of the first and second ring oscillators may be implemented with metal oxide semiconductor transistors. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20190305216
    Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization; an interconnect adjacent to the magnetic junction, wherein the interconnect comprises an antiferromagnetic (AFM) material which is doped with a doping material (Pt, Ni, Co, or Cr) and a structure adjacent to the interconnect such that the magnetic junction and the structure are on opposite surfaces of the interconnect, wherein the structure comprises a magnet with a second magnetization substantially different from the first magnetization.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Ian Young, Kevin O'Brien, Gary Allen, Noriyuki Sato
  • Publication number: 20190304525
    Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a magnetization (e.g., a perpendicular magnetization relative to an x-y plane of the apparatus); and an interconnect adjacent to the magnetic junction, wherein the interconnect comprises a chiral antiferromagnetic (AFM) material (e.g., Mn3X, where ‘X’ includes one of: Ge, Sn, Ga, Ir, Rh, or Pt; class-1 kagomi antiferromagnetic material, class-2 hyper kagomi antiferromagnetic material, or metallo-organics).
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Ian Young
  • Publication number: 20190305212
    Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Ian Young, Dmitri Nikonov, Chia-Ching Lin
  • Patent number: 10416217
    Abstract: Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Chia-Ching Lin, Yih Wang, Ian A. Young
  • Publication number: 20190273087
    Abstract: Described herein are ferroelectric memory cells and corresponding methods and devices. For example, in some embodiments, a ferroelectric memory cell disclosed herein includes one access transistor and one ferroelectric transistor (1T-1FE-FET cell). The access transistor is coupled to the ferroelectric transistor by sharing its source/drain terminal with that of the ferroelectric transistor and is used for both READ and WRITE access to the ferroelectric transistor.
    Type: Application
    Filed: December 12, 2016
    Publication date: September 5, 2019
    Applicant: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Publication number: 20190264997
    Abstract: This invention relates to a noise attenuation device and in particular a device which provides an increased performance in the range of a mortar system. A noise attenuation device suitable for use on a munition barrel, said device comprising an barrel extension portion, wherein the barrel extension portion has a length in the range of from 10 cm to 60 cm, at a first end of said barrel extension portion there is a tapered portion which tapers outwardly from said barrel extension portion, wherein said tapered portion, is frustroconical and has a cone angle in the range of from 22° to 28°, at a second end of the barrel extension portion a connector to secure the device onto a munition barrel.
    Type: Application
    Filed: October 5, 2017
    Publication date: August 29, 2019
    Applicant: BAE SYSTEMS plc
    Inventors: MARK EDWARD ROPER, CRAIG IAN YOUNG
  • Publication number: 20190259935
    Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.
    Type: Application
    Filed: December 23, 2016
    Publication date: August 22, 2019
    Inventors: Jasmeet S. CHAWLA, Sasikanth MANIPATRUNI, Robert L. BRISTOL, Chia-Ching LIN, Dmitri E. NIKONOV, Ian A. YOUNG
  • Publication number: 20190243662
    Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Applicant: Intel Corporation
    Inventors: Vaidyanathan KAUSHIK, Daniel H. MORRIS, Uygar E. AVCI, Ian A. YOUNG, Tanay KARNIK, Huichi LIU
  • Patent number: 10355005
    Abstract: Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Daniel H. Morris, Ian A. Young, Stephen M. Ramey
  • Patent number: 10347830
    Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Elijah Ilya Karpov, Brian Doyle, Dmitri E. Nikonov, Ian Young
  • Publication number: 20190198754
    Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10331582
    Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Ishwar S. Bhati, Huichu Liu, Jayesh Gaur, Kunal Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Hong Wang, Ian A. Young
  • Patent number: 10333523
    Abstract: Described is an apparatus which comprises: a first layer formed of a material that exhibits spin orbit torque effect; a second layer formed of material that exhibits spin orbit torque effect; and a magnetic tunneling junction (MTJ) including first and second free magnetic layers, wherein the first free magnetic layer is coupled to the first layer and wherein the second free magnetic layer is coupled to the second layer.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri Nikonov, Ian A. Young
  • Publication number: 20190189173
    Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 20, 2019
    Inventors: Sasikanth MANIPATRUNI, Ian YOUNG, Dmitri NIKONOV
  • Publication number: 20190181249
    Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
    Type: Application
    Filed: July 1, 2016
    Publication date: June 13, 2019
    Inventors: SASIKANTH MANIPATRUNI, ANURAG CHAUDHRY, DMITRI E. NIKONOV, JASMEET S. CHAWLA, CHRISTOPHER J. WIEGAND, KANWALJIT SINGH, UYGAR E. AVCI, IAN A. YOUNG
  • Patent number: 10320404
    Abstract: Described is an oscillating apparatus which comprises: an interconnect with spin-coupling material (e.g., Spin Hall Effect (SHE) material); and a magnetic stack having two magnetic layers such that one of the magnetic layers is coupled to the interconnect, wherein each of the two magnetic layers have respective magnetization directions to cause the magnetic stack to oscillate.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Sasi Manipatruni, George I. Bourianoff, Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20190169289
    Abstract: Disclosed herein are chimeric antigen receptor effector cells (CAR-ECs) and CAR-EC switches. The switchable CAR-ECs are generally T cells. The one or more chimeric antigen receptors may recognize a peptidic antigen on the CAR-EC switch. The CAR-ECs and switches may be used for the treatment of a condition in a subject in need thereof.
    Type: Application
    Filed: April 15, 2016
    Publication date: June 6, 2019
    Inventors: Travis YOUNG, David T. RODGERS, Ian HARDY, Chanhyuk KIM, Peter G. SCHULTZ, Eric HAMPTON, Eduardo LABORDA, Leonard PRESTA
  • Publication number: 20190138893
    Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip.
    Type: Application
    Filed: September 28, 2018
    Publication date: May 9, 2019
    Inventors: Abhishek SHARMA, Jack T. KAVALIEROS, Ian A. YOUNG, Ram KRISHNAMURTHY, Sasikanth MANIPATRUNI, Uygar AVCI, Gregory K. CHEN, Amrita MATHURIYA, Raghavan KUMAR, Phil KNAG, Huseyin Ekin SUMBUL, Nazila HARATIPOUR, Van H. LE