Patents by Inventor Ian A. Young
Ian A. Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11696514Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.Type: GrantFiled: December 29, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Benjamin Buford, Kaan Oguz, John J. Plombon, Ian A. Young
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Publication number: 20230200081Abstract: Described herein are integrated circuit devices formed using perovskite materials. Perovskite materials with a similar crystal structure and different electrical properties can be layered to realize a transistor or memory device. In some embodiments, a ferroelectric perovskite can be incorporated into a device with other perovskite films to form a ferroelectric memory device.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Arnab Sen Gupta, John J. Plombon, Dmitri E. Nikonov, Kevin P. O'Brien, Ian A. Young, Matthew V. Metz, Chia-Ching Lin, Scott B. Clendenning, Punyashloka Debashish, Carly Lorraine Rogan, Brandon Jay Holybee, Kaan Oguz
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Patent number: 11664305Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.Type: GrantFiled: June 27, 2019Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Kevin Lai Lin, Manish Chandhok, Miriam Reshotko, Christopher Jezewski, Eungnak Han, Gurpreet Singh, Sarah Atanasov, Ian A. Young
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Patent number: 11665975Abstract: An apparatus is provided which comprises: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; and a first device (e.g., a selector device) coupled at one end of the interconnect and to the second word-line; and a second device coupled to the magnetic junction, the first word-line and the source-line.Type: GrantFiled: June 19, 2018Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-Ching Lin, Sasikanth Manipatruni, Ian Young
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Patent number: 11651203Abstract: Embodiments may relate to a structure to be used in a neural network. A first column and a second column, both of which are to couple with a substrate. A capacitor structure may be electrically coupled with the first column. An insulator-metal transition (IMT) structure may be coupled with the first column such that the capacitor structure is electrically positioned between the IMT structure and the first column. A resistor structure may further be electrically coupled with the IMT structure and the second column such that the resistor structure is electrically positioned between the second column and the IMT structure. Other embodiments may be described or claimed.Type: GrantFiled: December 18, 2021Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Dmitri E. Nikonov, Elijah V. Karpov, Ian A. Young
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Patent number: 11646374Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.Type: GrantFiled: December 26, 2018Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Ashish Verma Penumatcha, Tanay Gosavi, Uygar Avci, Ian A. Young
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Patent number: 11646356Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.Type: GrantFiled: January 2, 2019Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Patent number: 11640984Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.Type: GrantFiled: March 25, 2019Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Jack Kavalieros, Ian Young, Matthew Metz, Uygar Avci, Chia-Ching Lin, Owen Loh, Seung Hoon Sung, Aditya Kasukurti, Sou-Chi Chang, Tanay Gosavi, Ashish Verma Penumatcha
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Patent number: 11637191Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.Type: GrantFiled: January 2, 2019Date of Patent: April 25, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Patent number: 11626451Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.Type: GrantFiled: June 17, 2019Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Emily Walker, Carl H. Naylor, Kaan Oguz, Kevin L. Lin, Tanay Gosavi, Christopher J. Jezewski, Chia-Ching Lin, Benjamin W. Buford, Dmitri E. Nikonov, John J. Plombon, Ian A. Young, Noriyuki Sato
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Patent number: 11626475Abstract: An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.Type: GrantFiled: June 14, 2019Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Nazila Haratipour, Chia-Ching Lin, Sou-Chi Chang, Ian A. Young, Uygar E. Avci, Jack T. Kavalieros
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Patent number: 11621391Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.Type: GrantFiled: December 28, 2018Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Kaan Oguz, Ian A. Young
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Publication number: 20230098594Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Chia-Ching LIN, Kaan OGUZ, Sou-Chi CHANG, Arnab SEN GUPTA, I-Cheng TUNG, Ian A. YOUNG, Matthew V. METZ, Uygar E. AVCI, Sudarat LEE
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Publication number: 20230101604Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional (3D) memory devices with transition metal dichalcogenide (TMD) channels. Other embodiments may be disclosed or claimed.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Ashish Verma PENUMATCHA, Uygar E. AVCI, Tanay GOSAVI, Shriram SHIVARAMAN, Carl H. NAYLOR, Chelsey DOROW, Ian A. YOUNG, Nazila HARATIPOUR, Kevin P. O'BRIEN
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Publication number: 20230102177Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to stacked MIM capacitors with multiple metal and dielectric layers that include insulating spacers on edges of one or more of the multiple layers to prevent unintended electrical coupling between metal layers during manufacturing. The dielectric layers may include Perovskite-based materials. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Chia-Ching LIN, Sou-Chi CHANG, Kaan OGUZ, I-Cheng TUNG, Arnab SEN GUPTA, Ian A. YOUNG, Uygar E. AVCI, Matthew V. METZ
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Patent number: 11616130Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.Type: GrantFiled: March 25, 2019Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Seung Hoon Sung, Jack Kavalieros, Ian Young, Matthew Metz, Uygar Avci, Devin Merrill, Ashish Verma Penumatcha, Chia-Ching Lin, Owen Loh
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Publication number: 20230090093Abstract: Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Ashish Verma PENUMATCHA, Uygar E. AVCI, Chelsey DOROW, Tanay GOSAVI, Chia-Ching LIN, Carl NAYLOR, Nazila HARATIPOUR, Kevin P. O'BRIEN, Seung Hoon SUNG, Ian A. YOUNG, Urusa ALAAN
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Patent number: 11605624Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.Type: GrantFiled: January 2, 2019Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
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Patent number: 11600659Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.Type: GrantFiled: August 11, 2021Date of Patent: March 7, 2023Assignee: INTEL CORPORATONInventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
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Patent number: 11594270Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device. In some embodiments, the apparatus comprises an interconnect partially adjacent to the structure of the magnetic junction, wherein the interconnect comprises a spin orbit material, wherein the interconnect has a pocket comprising non-spin orbit material, wherein the pocket is adjacent to the magnet of the magnetic junction. In some embodiments, the non-spin orbit material comprises metal which includes one or more of: Cu, Al, Ag, or Au.Type: GrantFiled: September 25, 2018Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Tanay Gosavi, Sasikanth Manipatruni, Chia-Ching Lin, Dmitri Nikonov, Christopher Wiegand, Ian Young