Patents by Inventor Ian A. Young

Ian A. Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PIEZO-RESISTIVE TRANSISTOR BASED RESONATOR WITH ANTI-FERROELECTRIC GATE DIELECTRIC
    Publication number: 20200212193
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation Santa Clara
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • FERROELECTRIC RESONATOR
    Publication number: 20200212532
    Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • ANTIFERROMAGNET BASED SPIN ORBIT TORQUE MEMORY DEVICE
    Publication number: 20200212291
    Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Chia-Ching LIN, Sasikanth MANIPATRUNI, Tanay GOSAVI, Dmitri NIKONOV, Kaan OGUZ, Ian A. YOUNG
  • INTEGRATION SCHEME FOR FERROELECTRIC MEMORY WITH A DEEP TRENCH STRUCTURE
    Publication number: 20200212055
    Abstract: A memory device comprises a trench within an insulating layer. A bottom electrode material is along sidewalls and a bottom of the trench, the bottom electrode material conformal to a top surface of the insulating layer. A ferroelectric material is conformal to the bottom electrode. A top electrode material is conformal to the ferroelectric material, wherein the bottom electrode material, the ferroelectric material and the top electrode material all extend above and across the top surface of the insulating layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Chia-Ching LIN, Sasikanth MANIPATRUNI, Tanay GOSAVI, Dmitri NIKONOV, Sou-Chi CHANG, Uygar E. AVCI, Ian A. YOUNG
  • PERPENDICULAR MAGNETOELECTRIC SPIN ORBIT LOGIC
    Publication number: 20200211608
    Abstract: An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.
    Type: Application
    Filed: December 13, 2016
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • PIEZO-RESISTIVE TRANSISTOR BASED RESONATOR WITH FERROELECTRIC GATE DIELECTRIC
    Publication number: 20200212194
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • FERROELECTRIC TRANSISTORS TO STORE MULTIPLE STATES OF RESISTANCES FOR MEMORY CELLS
    Publication number: 20200212224
    Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Inventors: Ashish Verma PENUMATCHA, Tanay GOSAVI, Uygar AVCI, Ian A. YOUNG
  • FERROELECTRICS USING THIN ALLOY OF PARA-ELECTRIC MATERIALS
    Publication number: 20200203358
    Abstract: Described is an apparatus which comprises: a first layer comprising a metal; a second layer comprising a first para-electric material, the second layer adjacent to the first layer; and a third layer comprising a second para-electric material, the third layer adjacent to the second layer, wherein the first para-electric material is different from the second para-electric material.
    Type: Application
    Filed: September 27, 2017
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Uygar E. Avci, Joshua M. Howard, Seiyon Kim, Ian A. Young
  • MAGNETIC CONTACTS FOR SPIN QUBITS
    Publication number: 20200194566
    Abstract: Systems, apparatus, and methods for initializing spin qubits with no external magnetic fields are described. An apparatus for quantum computing includes a quantum well and a pair of contacts. At least one of the contacts is formed of a ferromagnetic material. One of the contacts in the pair of contacts interfaces with a semiconductor material at a first position adjacent to the quantum well and the other contact in the pair of contacts interfaces with the semiconductor material at a second position adjacent to the quantum well. The ferromagnetic material initializes an electron or hole with a spin state prior to injection into the quantum well.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 18, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth MANIPATRUNI, Ravi PILLARISETTY, Dmitri E. NIKONOV, Ian A. YOUNG, James S. CLARKE
  • TRANSISTOR STRUCTURES FORMED WITH 2DEG AT COMPLEX OXIDE INTERFACES
    Publication number: 20200194576
    Abstract: Embodiments disclosed herein include transistor devices with complex oxide interfaces and methods of forming such devices. In an embodiment, the transistor device may comprise a substrate, and a fin extending up from the substrate. In an embodiment, a first oxide is formed over sidewall surfaces of the fin, and a second oxide is formed over the first oxide. In an embodiment, the first oxide and the second oxide are perovskite oxides with the general formula of ABO3.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Sasikanth MANIPATRUNI, Dmitri NIKONOV, Chia-Ching LIN, Tanay GOSAVI, Uygar AVCI, Ian YOUNG
  • COMBINATORIAL MAGNETO ELECTRIC SPIN ORBIT LOGIC
    Publication number: 20200194663
    Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Huichu Liu, Daniel Morris, Tanay Karnik, Sasikanth Manipatruni, Kaushik Vaidyanathan, Ian Young
  • Memory Including a Perovskite Material
    Publication number: 20200194444
    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Sou-Chi Chang, Uygar E. Avci, Ian A. Young
  • Ferroelectric Memory-Based Synapses
    Publication number: 20200194049
    Abstract: An embodiment includes an apparatus comprising: a first layer and a second layer; a first gate including first gate portions and a second gate including second gate portions; wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material; wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; wherein (a) a first plane intersects the first gate portions and the first and second layers, and (b) a second plane intersects the second gate portions and the first and second layers. Other embodiments are described herein.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Dmitri Nikonov, Ilya Karpov, Ian Young
  • Spin logic with spin hall electrodes and charge interconnects
    Patent number: 10679782
    Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Anurag Chaudhry, Ian A. Young
  • Noise attenuation device
    Patent number: 10670363
    Abstract: This invention relates to a noise attenuation device and in particular a device which provides an increased performance in the range of a mortar system. A noise attenuation device suitable for use on a munition barrel, said device comprising an barrel extension portion, wherein the barrel extension portion has a length in the range of from 10 cm to 60 cm, at a first end of said barrel extension portion there is a tapered portion which tapers outwardly from said barrel extension portion, wherein said tapered portion, is frustoconical and has a cone angle in the range of from 22° to 28°, at a second end of the barrel extension portion a connector to secure the device onto a munition barrel.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 2, 2020
    Assignee: BAE SYSTEMS PLC
    Inventors: Mark Edward Roper, Craig Ian Young
  • TUNNELING FIELD EFFECT TRANSISTORS
    Publication number: 20200168724
    Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.
    Type: Application
    Filed: August 18, 2017
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Ashish Agrawal, Benjamin Chu-Kung, Uygar E. Avci, Jack T. Kavalieros, Ian A. Young
  • PIEZORESISTIVE SELF-OSCILLATOR
    Publication number: 20200162024
    Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Raseong Kim, Sasikanth Manipatruni, Ian A. Young, Gary Alfred Allen, Tanay Gosavi
  • WIRELESS OSCILLATOR NEURAL NETWORK
    Publication number: 20200160145
    Abstract: Embodiments may relate to a system to be used in an oscillating neural network (ONN). The system may include a control node and a plurality of nodes wirelessly communicatively coupled with a control node. A node of the plurality of nodes may be configured to identify an oscillation frequency of the node based on a weight W and an input X. The node may further be configured to transmit a wireless signal to the control node, wherein a frequency of the wireless signal oscillates based on the identified oscillation frequency. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young
  • TRANSITION METAL DICHALCOGENIDE BASED SPIN ORBIT TORQUE MEMORY DEVICE WITH MAGNETIC INSULATOR
    Publication number: 20200161535
    Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching LIN, Tanay GOSAVI, Sasikanth MANIPATRUNI, Dmitri NIKONOV, Ian YOUNG
  • SEMICONDUCTOR DEVICES WITH METAL CONTACTS INCLUDING CRYSTALLINE ALLOYS
    Publication number: 20200152781
    Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 14, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry, Jasmeet S. Chawla, Ian A. Young