Patents by Inventor Ian D. Melville
Ian D. Melville has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8563416Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.Type: GrantFiled: July 29, 2011Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Brian Michael Erwin, Ian D. Melville, Ekta Misra, George John Scott
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Publication number: 20130273743Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.Type: ApplicationFiled: June 12, 2013Publication date: October 17, 2013Inventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
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Publication number: 20130234329Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: ApplicationFiled: April 30, 2013Publication date: September 12, 2013Applicant: Intetnational Business Machines CorporationInventors: Raschid J. BEZAMA, Timothy H. DAUBENSPECK, Gary LaFONTANT, Ian D. MELVILLE, Ekta MISRA, George J. SCOTT, Krystyna W. SEMKOW, Timothy D. SULLIVAN, Robin A. SUSKO, Thomas A. WASSICK, Xiaojin WEI, Steven L. WRIGHT
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Patent number: 8486814Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.Type: GrantFiled: July 21, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
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Patent number: 8446006Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: GrantFiled: December 17, 2009Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Raschid J. Bezama, Timothy H. Daubenspeck, Gary LaFontant, Ian D. Melville, Ekta Misra, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Robin A. Susko, Thomas A. Wassick, Xiaojin Wei, Steven L. Wright
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Patent number: 8445374Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.Type: GrantFiled: January 30, 2012Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca
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Publication number: 20130026624Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Michael Erwin, Ian D. Melville, Ekta Misra, George John Scott
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Publication number: 20130020682Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.Type: ApplicationFiled: July 21, 2011Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
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Publication number: 20120319246Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., RENESAS ELECTRONICS CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Soon Yoeng TAN, Teck Jung TANG, Ian D. MELVILLE, Yelei Vianna YAO, Yasushi YAMAGATA
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Publication number: 20120228748Abstract: A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.Type: ApplicationFiled: May 10, 2012Publication date: September 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: ALEXANDRE BLANDER, JON A. CASEY, TIMOTHY H. DAUBENSPECK, IAN D. MELVILLE, JENNIFER V. MUNCY, MARIE-CLAUDE PAQUET
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Patent number: 8236615Abstract: A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.Type: GrantFiled: November 25, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Alexandre Blander, Jon A Casey, Timothy H Daubenspeck, Ian D Melville, Jennifer V Muncy, Marie-Claude Paquet
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Publication number: 20120168952Abstract: Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.Type: ApplicationFiled: March 12, 2012Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Ian D. Melville, Krystyna W. Semkow
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Publication number: 20120168956Abstract: A method forms an integrated circuit structure, using a manufacturing device, to have kerf regions and external contacts, and to have conductive structures in the kerf regions. The method also forms an underfill material on a surface of the integrated circuit structure, using the manufacturing device, that contacts the kerf regions and the external contacts. The underfill material comprises electrically attracted filler particles that affect the coefficient of thermal expansion and elastic modulus of the underfill material. When forming the underfill material, the method applies an electrical charge to the conductive structures and the external contacts.Type: ApplicationFiled: January 4, 2011Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Stephane S. Barbeau, Catherine C. Dufort, Ian D. Melville, Luc L. Ouellet, Marie-Claude Paquet, Wolfgang Sauter, Jeffrey S. Zimmerman
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Publication number: 20120161300Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.Type: ApplicationFiled: March 1, 2012Publication date: June 28, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
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Publication number: 20120135564Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.Type: ApplicationFiled: January 30, 2012Publication date: May 31, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca
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Patent number: 8120175Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.Type: GrantFiled: November 30, 2007Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca
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Patent number: 8022543Abstract: A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.Type: GrantFiled: March 25, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Emily R. Kinser, Ian D. Melville
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Publication number: 20110193197Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MUKTA G. FAROOQ, JOHN A. GRIESEMER, WILLIAM F. LANDERS, IAN D. MELVILLE, THOMAS M. SHAW, HUILONG ZHU
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Publication number: 20110147922Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raschid J. BEZAMA, Timothy H. DAUBENSPECK, Gary LaFONTANT, Ian D. MELVILLE, Ekta MISRA, George J. SCOTT, Krystyna W. SEMKOW, Timothy D. SULLIVAN, Robin A. SUSKO, Thomas A. WASSICK, Xiaojin WEI, Steven L. WRIGHT
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Publication number: 20110121469Abstract: A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.Type: ApplicationFiled: November 25, 2009Publication date: May 26, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexandre Blander, Jon A. Casey, Timothy H. Daubenspeck, Ian D. Melville, Jennifer V. Muncy, Marie-Claude Paquet