Abstract: The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.

Abstract: A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

Abstract: The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.

Abstract: Chip location identification using dummy solder bead(s) is disclosed. A structure may include an integrated circuit (IC) chip including a plurality of solder beads for electrically coupling the IC chip to other structure, and a chip location identifier including at least one dummy solder bead on the IC chip, the chip location identifier representing a unique location of the IC chip in a wafer prior to dicing. The structure allows location tracking of an IC chip within a wafer without any additional processing, space, or mask levels. The structure can also be evaluated (visually or electrically) at the packaging level.

Abstract: Methods of forming an aluminum-free wire bond pad and the pad so formed are disclosed. In one embodiment, the method includes forming an opening through a dielectric layer to a last metal of a chip; forming a tantalum nitride (TaN) layer over the chip and over the opening; removing the tantalum nitride (TaN) layer outside of the opening; forming a passivation mask layer over the chip including a passivation mask opening over the last metal; forming a titanium tungsten (TiW) layer and a copper (Cu) layer over the chip; forming a mask layer over the chip including a mask opening to the copper (Cu) layer over the last metal; forming a nickel (Ni) layer and a copper (Cu) layer and then a gold (Au) layer in the mask opening; and removing the mask.

Abstract: Via stack structures are disclosed. In one embodiment, a structure includes a via stack including: a first substantially cross-shaped line in a first dielectric layer; a second substantially cross-shaped line set in a second dielectric layer, and a via stud coupling the first substantially cross-shaped line to the second substantially cross-shaped line. In another embodiment, a structure includes a first via stack, and a second via stack, wherein the first via stack and the second via stack extend in a divergent manner from one another. Each via stack structure is useful for support, for example, in under wire bond applications. The via stack structures can be mixed with other via stack structures and selectively placed within a layout to replace conventional metal plate and via stud array configurations.

Abstract: Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.