Abstract: Featured is a game applications programs, software, systems and methods that are such as to provide an interactive gaming experience for one or more game players by using speech recognition techniques in combination with interactive techniques and functionalities thereby as creating an interface that allows spoken words and/or phrases of a game player to initiate any one of a number of functionalities, actions or informational outputs in connection with the conduct of the game. Such methods, programs, and systems can further include creating an interface that allows a game player to initiate a function or action to be performed by the game player's character, to initiate a dialog or interaction between a player's character and a non-player character appearing in a game or to request information from a non-player character or about a phase of the game in general as part of the play of the game.

Abstract: A process of producing a clean substrate for use in semi-conductor processing in which the substrate is roughened to produce microfissures therein and then treated with a high concentration of a strong acid followed by coating with a material containing at least one metal oxide.

Abstract: A method for removing a metallic layer from the surface of a ceramic substrate, the method including the steps of immersing the metallic coated ceramic substrate in a solution of up to 31% hydrochloric acid for a sufficient time to at least substantially dissolve or remove the metallic layer therefrom, removing the ceramic substrate from the acid solution, rinsing the ceramic substrate in a rinse solution, and annealing the ceramic substrate at a predetermined temperature for a sufficient time to at least reduce damage or defects in the surface of the ceramic substrate.

Abstract: Entertainment-based methods and apparatus involving a video display facility and a lighting facility. In one example, lighting effects generated by the lighting facility are automatically coordinated with the video display facility. In another example, the lighting effects generated by the lighting facility are automatically coordinated with a video signal provided to the video display facility.

Abstract: A digital signal processing system for receiving from a Fourier Transform processor a first multiplicity of data points which together represent a Fourier Transform and processing the first multiplicity of data points to generate a second multiplicity of data points which together represent one or more other Fourier Transforms, comprises: a processing means for processing the first multiplicity of data points to generate the second multiplicity of data points by processing a plurality of pairs of data points of the first multiplicity of data points, each pair of data points comprising first and second data points that are to be processed together at the processing means.

Abstract: A data mining method and system for determining new relevant data from one or more data sources, the data of the data sources comprising pages of data linked together by links is described. The method comprises the steps of visiting the pages of data and obtaining links from the pages to other pages, processing the links in dependence on a predetermined set of rules to eliminate certain types of links, determining from the remaining links, links that existed on a previous visit to the page, eliminating previously existing links and preparing a report including the remaining links as potentially relevant data.

Abstract: A data classification method, data structure and associated systems are described. A number of hierarchical indices are defined and linked to data stored in a database. Data elements are linked to applicable ones of the indices in dependence on characteristics of the data. The link is with the lowest applicable entry in the respective index.

Abstract: The present invention provides a hinge for an orthopaedic knee brace comprising first and second hinge members rotatably connected together. The first hinge part is provided with an annular slot for receiving a pin provided on the second hinge member. First and second stop members are provided with opposed stop faces located in the region of the annular slot and are manually positionable circumferentially along the annular slot whereby to define a limited range of relative movement between the hinge members and a clamping member is provided for applying a clamping force to the stop members in a direction parallel to the axis of rotation of the hinge members, the stop members and the first hinge member having inter-engaging projections and recesses whereby to clamp the stop members to the first hinge member.

Abstract: Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruction set.

Abstract: A data processing system is described which has multiple sets of registers each of which is capable of autonomously controlling a common storage and common arithmetic and logic control circuits to execute respective tasks of a program. Level status blocks (LSBs), each assigned to a respective task, are held in main storage; and each contains such address and status data as is required for task execution in a controlled environment.

Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

Abstract: A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.

Abstract: The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data, and includes logic in a peripheral device control unit for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface.

Abstract: Combines a storage protect key stack with an access key register (AKR) and active access key (AAK) select circuits. Storage key entries in the stack correspond to the physical blocks in main memory. This combination can provide storage protection for different storage access types within address sub-ranges in the main memory associated with respective access keys. The sub-ranges are blocks of addresses within the full range of addresses of the physical memory. The protect key operation applies to physical addresses, and it obtains system addressing compatibility with an address translation operation using the same access keys as address keys with program logical addresses.Special features include a shared protect key, which need not be loaded in the AKR, to make specified sub-range(s) shareable by all users of the system, so that any user can access the blocks in memory associated with the shared protect key.

Abstract: Active address keys (AAK) are translated into respective addressabilities in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Each address key represents the assigned addressability in main memory for a logical address space. Plural key register sections may be loaded with the same or different address keys. For each storage access request, received from a processor or I/O channel, AAK select circuits outgate to the translator the key in the key register section corresponding to the type of the current storage access request to determine the addressability available to the access request. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block.

Abstract: A plurality of key register sections in a processor respectively associated with different machine-sensed types of accesses to a main storage of a computer system. A processor address key register (AKR) includes the following sections: (1) a section associated with an instruction-fetch type access, (2) a section associated with a source-operand fetch type access, and (3) a section associated with a sink-operand store/fetch type access. Other key register sections may be associated with respective sub-channel store/fetch type accesses. Circuits are provided which sense the different access types to select and outgate a key contained in the corresponding key register section.The values of the keys are associated with different addressabilities (i.e. address spaces). Each different key value is associated with a different stack of translation registers for containing the block addresses in real storage currently assigned to the respective addressabilities.

Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory.