Abstract: A network storage appliance is disclosed. The appliance includes a single chassis that encloses a plurality of servers and a plurality of storage controllers coupled together via a chassis backplane. The storage controllers control the transfer of data between the plurality of servers and a plurality of storage devices coupled to the storage controllers. The servers and storage controllers include a plurality of field replaceable unit (FRUs) hot-pluggable into the backplane such that any one of the FRUs may fail without loss of availability to the storage devices' data. In various embodiments, the chassis fits in a 19? wide rack; is 1U high; the servers are standard PCs configured to execute off-the-shelf server applications and to facilitate porting of popular operating systems with little modification; the servers include disk-on-chip memory rather than a hard drive; local buses (e.g., PCIX) on the backplane interface the various FRUs.

Abstract: An application server blade for an embedded storage appliance is disclosed. The blade includes a printed circuit board (PCB) with a connector for connecting to a chassis backplane including a local bus. Affixed on the PCB is a server, a portion of a storage controller, and an I/O link coupling the server and storage controller portion. The server transmits packets on the I/O link to the storage controller portion. The packets include commands to transfer data to a storage device controlled by the storage controller. The storage controller portion receives the packets from the server on the I/O link and forwards the commands on the backplane local bus to another portion of the storage controller affixed on a separate PCB also enclosed in the chassis. The blade also includes a removal mechanism for hot-replacement of the blade in the chassis. The blade architecture facilitates software reuse.

Abstract: An apparatus is disclosed for deterministically performing active-active failover of redundant servers in response to a failure of a link on which each server provides a heartbeat to the other server. Each of the servers is configured to take over the identity of the other server on a common network in response to detecting a failure of the other server's link heartbeat. Each server provides a status indicator to a storage controller indicating whether the other server's link heartbeat stopped. The storage controller determines the link has failed if both of the status indicators indicate the other server's heartbeat stopped, and responsively kills one of the servers. The storage controller also receives a heartbeat directly from each server. If only one direct heartbeat stops when the status indicators indicate the link heartbeats stopped, then the storage controller detects one server has failed and inactivates the failed server.

Abstract: A network storage appliance is disclosed. The appliance includes a chassis enclosing a backplane, and a server enclosed in the chassis and coupled to the backplane. The appliance also includes storage controllers enclosed in the chassis, each coupled to the backplane, which control transfer of data between the server and storage devices coupled to the storage controllers. The storage controllers also control transfer of data between the storage devices and computers networked to the appliance and external to the appliance. The storage controllers and the server comprise a plurality of hot-replaceable blades. Any one of the plurality of blades may be replaced during operation of the appliance without loss of access to the storage devices by the computers. In one embodiment, the server executes storage application software, such as backup software for backing up data on the storage devices, such as to a tape device networked to the server.

Abstract: A digital signal processing system for receiving from a Fourier Transform processor a first multiplicity of data points which together represent a Fourier Transform and processing the first multiplicity of data points to generate a second multiplicity of data points which together represent one or more other Fourier Transforms, comprises: a processing means for processing the first multiplicity of data points to generate the second multiplicity of data points by processing a plurality of pairs of data points of the first multiplicity of data points, each pair of data points comprising first and second data points that are to be processed together at the processing means.

Abstract: A data mining method and system for determining new relevant data from one or more data sources, the data of the data sources comprising pages of data linked together by links is described. The method comprises the steps of visiting the pages of data and obtaining links from the pages to other pages, processing the links in dependence on a predetermined set of rules to eliminate certain types of links, determining from the remaining links, links that existed on a previous visit to the page, eliminating previously existing links and preparing a report including the remaining links as potentially relevant data.

Abstract: Polymorphic, amorphous and hydrated forms of the title compound having the following structure: are disclosed. The compound is a potent and selective cyclooxygenase-2 (COX-2) inhibitor.

Abstract: A data classification method, data structure and associated systems are described. A number of hierarchical indices are defined and linked to data stored in a database. Data elements are linked to applicable ones of the indices in dependence on characteristics of the data. The link is with the lowest applicable entry in the respective index.

Abstract: cis-aminochromanols are obtained in high yield and with high selectivity over their trans counterparts by hydrogenating the corresponding oximes in the presence of a catalyst and an acid selected from HBr, HCl, and organic sulfonic acid. The cis-aminochromanols can be employed as intermediates in the production of HIV protease inhibitors which are useful for treating HIV infection and AIDS.

Abstract: cis-aminochromanols are obtained in high yield and with high selectivity over their trans counterparts by hydrogenating the corresponding oximes in the presence of a catalyst and an acid selected from HBr, HCl, and organic sulfonic acid. The cis-aminochromanols can be employed as intermediates in the production of HIV protease inhibitors which are useful for treating HIV infection and AIDS.

Abstract: The invention encompasses a process for making compounds of Formula I useful in the treatment of cyclooxygenase-2 mediated diseases.

Abstract: The present invention provides a hinge for an orthopaedic knee brace comprising first and second hinge members rotatably connected together. The first hinge part is provided with an annular slot for receiving a pin provided on the second hinge member. First and second stop members are provided with opposed stop faces located in the region of the annular slot and are manually positionable circumferentially along the annular slot whereby to define a limited range of relative movement between the hinge members and a clamping member is provided for applying a clamping force to the stop members in a direction parallel to the axis of rotation of the hinge members, the stop members and the first hinge member having inter-engaging projections and recesses whereby to clamp the stop members to the first hinge member.

Abstract: A method of fabricating two terminal mesa semiconductor devices comprising etching a surface doped and metal coated silicon slice thereby to form a plurality of silicon frusta each capped by a metal contact pad, covering the frusta side of the slice with a metal contact continuity layer and then with a handle layer formed to lie parallel with that surface of the silicon slice which is remote from the frusta, lapping away the silicon slice to expose parts of the handle layer which extend between the frusta so that the frusta are separated so as to define discrete mesas held together by the handle layer, forming one of the two terminals on a face of the mesas remote from the contact pads, removing the handle layer to reveal the contact pads and bonding each contact pad thereby revealed to the metallized face of a diamond heat sink, one heat sink to each contact pad, which heat sink forms a part of the other of the two terminals of each mesa semiconductor device.

Abstract: A method of making a diamond heatsink includes securing a number of spaced diamonds to a sacrificial plate and then metallizing them with, for example, a thin layer of gold, silver, copper or aluminium. The plate and the diamonds are subsequently metal plated with a similar metal to the metallization until the diamonds are completely covered. The sacrificial plate is removed and the exposed surface cleaned and polished. Finally the assembly is diced to produce a number of individual heatsink assemblies.

Abstract: Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruction set.

Abstract: A data processing system is described which has multiple sets of registers each of which is capable of autonomously controlling a common storage and common arithmetic and logic control circuits to execute respective tasks of a program. Level status blocks (LSBs), each assigned to a respective task, are held in main storage; and each contains such address and status data as is required for task execution in a controlled environment.

Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

Abstract: A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.

Abstract: Combines a storage protect key stack with an access key register (AKR) and active access key (AAK) select circuits. Storage key entries in the stack correspond to the physical blocks in main memory. This combination can provide storage protection for different storage access types within address sub-ranges in the main memory associated with respective access keys. The sub-ranges are blocks of addresses within the full range of addresses of the physical memory. The protect key operation applies to physical addresses, and it obtains system addressing compatibility with an address translation operation using the same access keys as address keys with program logical addresses.Special features include a shared protect key, which need not be loaded in the AKR, to make specified sub-range(s) shareable by all users of the system, so that any user can access the blocks in memory associated with the shared protect key.

Abstract: The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data, and includes logic in a peripheral device control unit for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface.