Abstract: Provided is a method for producing an alkenyl phosphorus compound which can produce an alkenyl phosphorus compound efficiently even with a smaller amount of a catalyst used than that used conventionally, and further which can maintain catalytic activity to produce an alkenyl phosphorus compound in high yield even at a larger reaction scale, and which can also be applied to quantity synthesis at an industrial scale using a conventional batch reactor or continuous reactor. A method for producing an alkenyl phosphorus compound, comprising: a step of reacting a compound represented by the following formula (1): [In formula (1), R1 represents OR3 or R3, R2 represents OR4 or R4, and R3 and R4 represent, for example, each independently a substituted or unsubstituted alkyl group.] with a compound represented by the following formula (2): [In formula (2), R5 represents, for example, a hydrogen atom, or a substituted or unsubstituted alkyl group.

Abstract: Provided is a method for producing an alkenyl phosphorus compound which can produce an alkenyl phosphorus compound efficiently even with a smaller amount of a catalyst used than that used conventionally, and further which can maintain catalytic activity to produce an alkenyl phosphorus compound in high yield even at a larger reaction scale, and which can also be applied to quantity synthesis at an industrial scale using a conventional batch reactor or continuous reactor. A method for producing an alkenyl phosphorus compound, comprising: a step of reacting a compound represented by the following formula (1): [In formula (1), R1 represents OR3 or R3, R2 represents OR4 or R4, and R3 and R4 represent, for example, each independently a substituted or unsubstituted alkyl group.] with a compound represented by the following formula (2): R5—C?CH??(2) [In formula (2), R5 represents, for example, a hydrogen atom, or a substituted or unsubstituted alkyl group.

Abstract: The present invention provides a novel oral administration preparation that enables administration of silodosin, which is a drug with extremely strong bitterness, without a foreign-body sensation even without water, and has dissolution properties of being able to reproduce an effective blood concentration for the treatment of dysuria associated with benign prostatic hyperplasia or the like. The present invention relates to a masked particle and a novel oral administration preparation comprising the masked particle or the like, wherein the masked particle obtained by granulating or coating a drug particle comprising a fine powder of silodosin with a coating agent comprising a non-enteric polymer, and a content of the non-enteric polymer is 80 parts by mass to 400 parts by mass relative to 100 parts by mass of silodosin.

Abstract: A three phase inverter-type generator includes an engine, an AC generator driven by the engine, a rectifier for converting the output of the AC generator into a DC voltage, a three phase inverter for converting the output of the rectifier into a three phase AC voltage, a three phase transformer connected to the output side of the three phase inverter, and a filter, whereby the three phase transformer has a primary-side connection and a secondary-side connection having a three phase connection, the secondary-side connection having first through third windings forming a star connection in which one end of each is respectively connected to a neutral point, with each having the same number of windings and a mutual phase difference of 120°.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: A three phase inverter-type generator includes an engine, an AC generator driven by the engine, a rectifier for converting the output of the AC generator into a DC voltage, a three phase inverter for converting the output of the rectifier into a three phase AC voltage, a three phase transformer connected to the output side of the three phase inverter, and a filter, whereby the three phase transformer has a primary-side connection and a secondary-side connection having a three phase connection, the secondary-side connection having first through third windings forming a star connection in which one end of each is respectively connected to a neutral point, with each having the same number of windings and a mutual phase difference of 120°.

Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

Abstract: A valve timing control apparatus includes a driving rotation member, a driven rotation member, an advance angle chamber displacing a rotation phase of the driven rotation member relative to the driving rotation member in an advance angle direction, a retard angle chamber displacing the relative rotation phase in a retard angle direction, a groove provided on at least one of an inner surface of the driving rotation member and an outer surface of the driven rotation member for supplying the hydraulic fluid to a sliding contact portion formed by the inner surface of the driving rotation member and the outer surface of the driven rotation member, an advance angle oil passage, a retard angle oil passage, and a groove oil passage for supplying the hydraulic fluid to the groove.

Abstract: A process for producing a high-purity vinyl ether, which comprises: a step of subjecting an alcohol represented by the general formula (1) R—O—H??(1) to a vinyl ether formation reaction in the presence of a catalyst to synthesize a vinyl ether represented by the general formula (2), R—O—CH?CH2??(2) a step of removing the catalyst from the reaction mixture obtained in the above step to obtain a crude vinyl ether containing the vinyl ether and the unreacted raw material alcohol, a step of reacting the unreacted raw material alcohol in the crude vinyl ether, with the vinyl ether in the presence of an acid catalyst, to convert the alcohol into an acetal represented by the general formula (3), and a step of subjecting a crude vinyl ether containing the acetal (III) to distillation to obtain a high-purity vinyl ether.

Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: A valve timing control apparatus includes a driving rotation member, a driven rotation member, an advance angle chamber displacing a rotation phase of the driven rotation member relative to the driving rotation member in an advance angle direction, a retard angle chamber displacing the relative rotation phase in a retard angle direction, a groove provided on at least one of an inner surface of the driving rotation member and an outer surface of the driven rotation member for supplying the hydraulic fluid to a sliding contact portion formed by the inner surface of the driving rotation member and the outer surface of the driven rotation member, an advance angle oil passage, a retard angle oil passage, and a groove oil passage for supplying the hydraulic fluid to the groove.

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.

Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.