Patents by Inventor Ichiro Mihara

Ichiro Mihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7692282
    Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 6, 2010
    Assignee: Casio Computer Co., Ltd
    Inventors: Shinji Wakisaka, Hiroyasu Jobetto, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20100019383
    Abstract: In this manufacturing method of a semiconductor device, a metal plate having a plurality of projection electrodes in each of a plurality of semiconductor device formation areas is prepared. Next, the projection electrodes of each of the semiconductor formation areas are aligned corresponding to external connection electrodes of each semiconductor construction, and each semiconductor construction is separately arranged on the projection electrodes in the semiconductor device formation areas. Next, an insulating layer formation sheet is arranged on the metal plate, and the metal plate and the insulating layer formation sheet are joined by heat pressing. Then, the metal plate is patterned and a plurality of upper layer wirings that connect to the projection electrodes is formed.
    Type: Application
    Filed: July 21, 2009
    Publication date: January 28, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Ichiro MIHARA, Takeshi Wakabayashi
  • Patent number: 7618886
    Abstract: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: November 17, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Jobetto, Ichiro Mihara
  • Patent number: 7592672
    Abstract: A circuit substrate of a grounding structure of a semiconductor device according to the invention has a plurality of connection pads and a grounding wiring. The semiconductor device has a semiconductor substrate having one side face and the other side face opposite thereto, an insulating film formed thereon, an SOI integrated circuit provided thereon and including a plurality of connection pads, and electrodes for external connection each of which is connected to the corresponding connection pad. The semiconductor device has the external connection electrodes connected to the respective connection pads of the circuit substrate by a face-down bonding scheme. An under-filling material is provided between the semiconductor device and the circuit substrate, and there is provided a connection member which connects the other side face of the semiconductor device with the grounding wiring of the circuit substrate, and is made of a conductive material.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: September 22, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara, Osamu Okada
  • Publication number: 20090200665
    Abstract: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly.
    Type: Application
    Filed: March 31, 2009
    Publication date: August 13, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Jobetto, Ichiro Mihara
  • Patent number: 7563640
    Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: July 21, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinji Wakisaka, Hiroyasu Jobetto, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20090174062
    Abstract: A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the through holes. Bottom surfaces of the bottomed cylindrical portions of the wiring lines serve as connection pad portions.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 9, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventor: Ichiro MIHARA
  • Patent number: 7550833
    Abstract: A semiconductor device comprises a plurality of semiconductor constructions being mutually laminated each having a semiconductor substrate and a plurality of external connection electrodes arranged on the semiconductor substrate respectively, an insulating layer formed around the peripheries of the semiconductor constructions, an upper layer insulating film formed on an uppermost one of the semiconductor constructions and the insulating layer, and upper layer wirings arranged on the upper layer insulating film by electrically connecting to the external connection electrodes of semiconductor constructions.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: June 23, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Patent number: 7550843
    Abstract: A semiconductor device includes a base member made of a material containing at least a thermosetting resin, and at least one semiconductor constructing body mounted on the base member, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base member around the semiconductor constructing body. An interconnection of at least one layer is formed on one sides of the semiconductor constructing body and insulating layer, electrically connected to the external connecting electrode of the semiconductor constructing body, and having a connecting pad portion, the semiconductor substrate is fixed to the base member by fixing force of the base member.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: June 23, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Patent number: 7547967
    Abstract: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: June 16, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Jobetto, Ichiro Mihara
  • Patent number: 7528480
    Abstract: A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the through holes. Bottom surfaces of the bottomed cylindrical portions of the wiring lines serve as connection pad portions.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: May 5, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Patent number: 7514335
    Abstract: A method of manufacturing a semiconductor device includes providing a base plate; mounting a plurality of semiconductor chips, the plural semiconductor chips being mounted apart from each other; forming an insulating film on an upper surface of the base; forming a plurality of pairs of re-wirings on the insulating film, each of the re-wirings being connected to a connection pad of any of the semiconductor chips the insulating film formed on the periphery of the semiconductor chip, and the re-wiring having a pad portion arranged in the region of the insulating film.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: April 7, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20090079073
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Application
    Filed: June 4, 2008
    Publication date: March 26, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20090079072
    Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit. A low dielectric film wiring line laminated structure portion is provided on the semiconductor substrate except a peripheral portion thereof, and is constituted by low dielectric films and wiring lines. The low dielectric film has a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the laminated structure portion. A connection pad portion is arranged on the insulating film and connected to a connection pad portion of an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film is provided on the insulating film which surrounds the pump electrode and on the peripheral portion of the semiconductor substrate. The side surfaces of the laminated structure portion are covered with the insulating film or the sealing film.
    Type: Application
    Filed: December 13, 2007
    Publication date: March 26, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20090065926
    Abstract: A semiconductor device includes a base plate made of a material including at least a thermosetting resin, and having an opening, a vertical conductor filled and provided in the opening of the base plate, at least one semiconductor construct having a semiconductor substrate and a plurality of external connection electrodes provided on one side of the semiconductor substrate, and an insulating layer secured to and provided on a periphery of the semiconductor construct. The insulating layer is secured to the base plate, and the external connection electrodes of the semiconductor construct are bonded to the vertical conductor.
    Type: Application
    Filed: October 31, 2008
    Publication date: March 12, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Takeshi WAKABAYASHI, Ichiro Mihara
  • Patent number: 7459340
    Abstract: A semiconductor device includes a base plate made of a material including at least a thermosetting resin, and having an opening, a vertical conductor filled and provided in the opening of the base plate, at least one semiconductor construct having a semiconductor substrate and a plurality of external connection electrodes provided on one side of the semiconductor substrate, and an insulating layer secured to and provided on a periphery of the semiconductor construct. The insulating layer is secured to the base plate, and the external connection electrodes of the semiconductor construct are bonded to the vertical conductor.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: December 2, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20080286903
    Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.
    Type: Application
    Filed: July 17, 2008
    Publication date: November 20, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7445964
    Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: November 4, 2008
    Assignees: Casio Computer Co., Ltd., CMK Corporation
    Inventors: Ichiro Mihara, Takeshi Wakabayashi, Toshihiro Kido, Hiroyasu Jobetto, Yutaka Yoshino, Nobuyuki Kageyama, Daita Kohno, Jun Yoshizawa
  • Publication number: 20080203526
    Abstract: A plurality of wirings, column-shaped electrodes, sealing films, and soldering balls, are provided on a third upper-layer insulating film formed on a silicon substrate. A spirally configured thin-film inductive element is disposed beneath the bottom surface of a ground insulating film formed beneath the silicon substrate. The inner and outer end portions of the thin-film inductive element are respectively connected to the wirings via a vertical conductor disposed in the silicon substrate. In this case, it is not required to secure a certain area otherwise needed for the formation of the thin-film inductive element over the surface of the third upper-layer insulating film that accommodates the wirings. Hence, even when the thin-film inductive element has been provided, it is possible to evade a feasibility to incur restraint on the distribution of the wirings formed over the surface of the third upper-layer insulating film.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 28, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Patent number: 7417330
    Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: August 26, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara