Patents by Inventor Ichiro Mihara

Ichiro Mihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080191357
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of wiring lines which are provided on one side of the semiconductor substrate and which have connection pad portions, and a plurality of columnar electrodes respectively provided on the connection pad portions of the wiring lines, each of the columnar electrodes including an outer peripheral surface and a top surface. An electromigration prevention film is provided on at least the surfaces of the wiring lines. A sealing film is provided around the outer periphery surfaces of the columnar electrodes.
    Type: Application
    Filed: January 22, 2008
    Publication date: August 14, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventors: Ichiro Kouno, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7390688
    Abstract: A semiconductor device includes a semiconductor substrate which has an integrated circuit formed on a front surface thereof, and a rough surface with a height difference of 1 to 5 ?m on a rear surface thereof. A protective film is provided on the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: June 24, 2008
    Assignee: Casio Computer Co.,Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7378645
    Abstract: An optical sensor with an upper surface having a photoelectric conversion device area and connection pads connected to the photoelectric conversion device area thereof; a semiconductor structure which has a plurality of electrodes for external connection; an insulating layer formed on the periphery of the semiconductor structure; and a first wiring formed on at least one of the semiconductor structure and the optical sensor and connecting at least one of the electrodes for external connection of the semiconductor structure to one of the connection pads of the optical sensor.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: May 27, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ichiro Mihara, Hiroyasu Jobetto
  • Patent number: 7368813
    Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: May 6, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinji Wakisaka, Hiroyasu Jobetto, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20080044944
    Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.
    Type: Application
    Filed: September 11, 2007
    Publication date: February 21, 2008
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Shinji WAKISAKA, Hiroyasu Jobetto, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20080006943
    Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.
    Type: Application
    Filed: September 11, 2007
    Publication date: January 10, 2008
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Shinji WAKISAKA, Hiroyasu Jobetto, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7294922
    Abstract: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: November 13, 2007
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Jobetto, Ichiro Mihara
  • Publication number: 20070228468
    Abstract: A circuit substrate of a grounding structure of a semiconductor device according to the invention has a plurality of connection pads and a grounding wiring. The semiconductor device has a semiconductor substrate having one side face and the other side face opposite thereto, an insulating film formed thereon, an SOI integrated circuit provided thereon and including a plurality of connection pads, and electrodes for external connection each of which is connected to the corresponding connection pad. The semiconductor device has the external connection electrodes connected to the respective connection pads of the circuit substrate by a face-down bonding scheme. An under-filling material is provided between the semiconductor device and the circuit substrate, and there is provided a connection member which connects the other side face of the semiconductor device with the grounding wiring of the circuit substrate, and is made of a conductive material.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 4, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara, Osamu Okada
  • Patent number: 7247947
    Abstract: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating layer. Upper layer wiring lines are provided on the upper layer insulating film so that the upper layer wiring line is electrically connected to the external connection electrode. A second semiconductor construct is joined to and installed on connection pad portions. All jointing portions of the second semiconductor construct for the connection pad portions of the upper layer wiring lines are disposed in a region corresponding to the first semiconductor construct.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: July 24, 2007
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20070158857
    Abstract: A semiconductor device includes a plurality of semiconductor constructs, each of the semiconductor constructs including a semiconductor substrate and external connection electrodes provided on an upper surface of the semiconductor substrate. The semiconductor substrates of the semiconductor constructs are different in a planar-size. The plurality of semiconductor constructs are stacked from bottom to top in descending order of planar-sizes of the semiconductor substrates included in the plurality of semiconductor constructs. An insulating film at least is provided around one semiconductor construct disposed on the top of the plurality of semiconductor constructs and on another semiconductor construct disposed under the one semiconductor construct. Each of the upper surfaces of the plurality of external connection electrodes is exposed from the one semiconductor construct and from the insulating film.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 12, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Publication number: 20070145518
    Abstract: A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the through holes. Bottom surfaces of the bottomed cylindrical portions of the wiring lines serve as connection pad portions.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 28, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Publication number: 20070126127
    Abstract: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly.
    Type: Application
    Filed: February 5, 2007
    Publication date: June 7, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Jobetto, Ichiro Mihara
  • Publication number: 20070126128
    Abstract: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly.
    Type: Application
    Filed: February 5, 2007
    Publication date: June 7, 2007
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Hiroyasu Jobetto, Ichiro Mihara
  • Publication number: 20070123022
    Abstract: There is prepared a semiconductor construction in which a plurality of columnar electrodes are provided on an upper side of a semiconductor substrate and in which a sealing film is provided on the semiconductor substrate to cover outer peripheral surfaces of the columnar electrodes. Upper sides of the columnar electrodes are removed to form openings in the sealing film on the supper sides of the columnar electrodes. Adhesive coatings are formed on upper surfaces of the columnar electrodes in the openings of the sealing film, Solder balls are provided on upper surfaces of the adhesive coatings. Finally, the solder balls are deformed by a heat treatment to form solder bumps in and above the openings of the sealing film so that the solder bumps are connected to the upper surfaces of the columnar electrodes. Thus, a semiconductor device is manufactured.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 31, 2007
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20070099409
    Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.
    Type: Application
    Filed: December 13, 2006
    Publication date: May 3, 2007
    Applicants: Casio Computer Co., Ltd., CMK Corporation
    Inventors: Ichiro Mihara, Takeshi Wakabayashi, Toshihiro Kido, Hiroyasu Jobetto, Yutaka Yoshino, Nobuyuki Kageyama, Daita Kohno, Jun Yoshizawa
  • Publication number: 20070069272
    Abstract: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating layer. Upper layer wiring lines are provided on the upper layer insulating film so that the upper layer wiring line is electrically connected to the external connection electrode. A second semiconductor construct is joined to and installed on connection pad portions. All jointing portions of the second semiconductor construct for the connection pad portions of the upper layer wiring lines are disposed in a region corresponding to the first semiconductor construct.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 29, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7190064
    Abstract: A plurality of semiconductor chips (23) are bonded to an adhesive layer (22) formed on a base plate (21). Then, first to third insulating films (31, 35, 39), first and second underlying metal layers (33, 37), first and second re-wirings (34, 38), and a solder ball (41) are collectively formed for the plural semiconductor chips (23). In this case, the first and second underlying metal layers (33, 37) are formed by a sputtering method, and the first and second re-wirings (34, 38) are formed by an electroplating method. Then, a laminate structure consisting of the three insulating films (39, 35, 31), the adhesive layer (22), and the base plate (21) is cut in a region positioned between the adjacent semiconductor chips (23).
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: March 13, 2007
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7183639
    Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: February 27, 2007
    Assignees: Casio Computer Co., Ltd., CMK Corporation
    Inventors: Ichiro Mihara, Takeshi Wakabayashi, Toshihiro Kido, Hiroyasu Jobetto, Yutaka Yoshino, Nobuyuki Kageyama, Daita Kohno, Jun Yoshizawa
  • Publication number: 20070042594
    Abstract: A method of manufacturing a semiconductor device includes providing a base plate; mounting a plurality of semiconductor chips each having a plurality of connection pads formed on an upper surface thereof to the base plate, the plural semiconductor chips being mounted apart from each other; forming an insulating film on an upper surface of the base plate including the upper surfaces of the semiconductor chips such that the insulating film has a flat surface; forming a plurality of pairs of re-wirings on the insulating film, each of the re-wirings being connected to a connection pad of any of the semiconductor chips and at least some of the re-wirings having pad portions arranged in a region of the insulating film formed on the periphery of the semiconductor chip connected to the connection pad; and cutting the insulating film between the adjacent semiconductor chips so as to obtain a plurality of semiconductor devices each comprising at least one semiconductor chip, the insulating film formed on the periphery
    Type: Application
    Filed: October 27, 2006
    Publication date: February 22, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20060273463
    Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit, a first insulating film formed on the semiconductor substrate, at least one power source internal wiring line formed on the first insulating film, and a second insulating film formed on the first insulating film and on the internal wiring line and having a plurality of openings exposing parts of the internal wiring line. At least one wiring line is formed on an upper side of the second insulating film to correspond to the internal wiring line and electrically connected to the internal wiring line via the plurality of openings of the second insulating film. The wiring line has at least one external electrode pad portion whose number is smaller than the number of openings in the second insulating film.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 7, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventors: Takeshi Wakabayashi, Ichiro Mihara