Patents by Inventor Ichiro Mihara

Ichiro Mihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030038331
    Abstract: In a semiconductor device such as a CSP, re-wiring is provided on a circuit element formation region of a semiconductor substrate and a columnar electrode for connection with a circuit board is provided on the re-wiring. A first insulating film is provided over the semiconductor substrate excluding a connection pad, and a ground potential layer connected to a ground potential is provided on an upper surface of the first insulating film on the circuit element formation region. A re-wiring is provided over the ground potential layer with a second insulating film interposed. Since the ground potential layer serves as a barrier layer for preventing crosstalk between the re-wiring and circuit element formation region, it is possible to eliminate crosstalk between the re-wiring and a circuit within the circuit element formation region and to freely position the re-wiring without restrictions. Furthermore, a thin-film circuit element may be provided at a given location on the second insulating film.
    Type: Application
    Filed: September 25, 2002
    Publication date: February 27, 2003
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Yutaka Aoki, Ichiro Mihara, Takeshi Wakabayashi, Katsumi Watanabe
  • Patent number: 6501169
    Abstract: A semiconductor device of a CSP structure is obtained by forming projection electrodes on a plurality of circuit element forming areas of a semiconductor wafer substrate, and then dividing the wafer into chips. Wiring patterns connected to connection pads for signal transmission are provided on the upper surface of an insulating film formed on the circuit element forming areas, and a conductive layer connected to a connection pad connected to a ground potential is provided on the resultant structure except for on the wiring patterns and on areas near the wiring patterns. Further, a thin film circuit element may be provided at the same layer as the conductive layer or below the conductive layer.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: December 31, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Yutaka Aoki, Hiroshi Takenaka, Ichiro Mihara
  • Patent number: 6467674
    Abstract: A sealing film is formed on a semiconductor substrate on which a number of columnar electrodes are formed, and then the upper surface of the sealing film is polished to expose the upper surfaces of the columnar electrodes made of a soft metal. During the polishing, laterally broadened edges are generated on the upper sides of the columnar electrodes. Then, the upper surfaces of the columnar electrodes, including the laterally broadened edges, are etched so as to remove the edges. In this manner, the shape of the upper surfaces of the columnar electrodes can be formed as initially designed, and therefore the bonding strengths can be made uniform. Thus, the reliability of the device can be improved.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: October 22, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Publication number: 20020017730
    Abstract: A thin film passive element includes at least one of a capacitance element having a plurality of conductive layers and a dielectric material layer and an inductance element formed of a patterned conductive layer is stacked on a circuit element-forming region of a semiconductor substrate provided with a plurality of connection pads and is connected to the circuit element of the circuit element-forming region.
    Type: Application
    Filed: August 8, 2001
    Publication date: February 14, 2002
    Applicant: Integrated Electronics & Packaging
    Inventors: Iwao Tahara, Ichiro Mihara, Yutaka Aoki
  • Publication number: 20020000658
    Abstract: A semiconductor device includes a semiconductor substrate having bump electrodes and a sealing film formed thereon, the sealing film having laminated layers. The semiconductor device is mounted to another circuit substrate via the bump electrodes. The sealing film interposed between adjacent bump electrodes is prepared by laminating a protective film and each layer of the sealing film on the lower surface of the base film, on the bump electrodes, followed by allowing the bump electrodes to project through the sealing film under pressure and heat. The thickness of the sealing film is smaller than the height of the bump electrode, and thus the bump electrode projects through the sealing film. The stress derived from the difference in thermal expansion coefficient between the semiconductor substrate and the circuit substrate is absorbed by the projecting portion of the bump electrode.
    Type: Application
    Filed: January 31, 2000
    Publication date: January 3, 2002
    Inventors: Osamu Kuwabara, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 6319851
    Abstract: A resin sealing film is formed on a silicon substrate by using a printing mask and a squeegee. The side surface in the tip portion of the squeegee is substantially V-shaped, and the printing is performed by pushing the tip portion of the squeegee into the gap between adjacent bump electrodes. As a result, the sealing film is formed in a manner to be depressed in the region between adjacent bump electrodes so as to facilitate the swinging movement of the bump electrodes. It follows that, in a temperature cycle test performed after the silicon substrate is mounted to a circuit substrate, the stress derived from the difference in thermal expansion coefficient between the silicon substrate and the circuit substrate is absorbed by the bump electrode.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: November 20, 2001
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ichiro Mihara, Osamu Kuwabara
  • Patent number: 6140155
    Abstract: A plating tray includes a recessed region in a central portion of an insulating substrate for arranging therein a silicon semiconductor substrate and a metal film arranged to surround the recessed region. The semiconductor substrate is housed in the recessed region. Under this condition, a dry photoresist film containing Na, K, Ca and Cu in amounts smaller than predetermined amounts is formed to cover a metal underlying film. Then, a projecting electrode is formed by electroplating within open portions formed in the resist film. In forming the projecting electrode, the open portion is also formed in that region of the resist film which corresponds to the metal film of the plating plate so as to form a dummy projection electrode simultaneously.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: October 31, 2000
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ichiro Mihara, Shoichi Kotani, Takeshi Wakabayashi, Masami Hiramoto
  • Patent number: 5739392
    Abstract: Acrylic acid can be produced efficiently by subjecting acrolein to catalytic gas-phase oxidation in the presence of a molybdenum/vanadium-based oxide catalyst prepared by using particular substances as the raw materials of the individual metal elements constituting the catalyst. A preferable example of such a catalyst is prepared by using, as the raw materials of vanadium, ammonium metavanadate and at least one vanadium oxide in which the valency of vanadium is larger than 0 but smaller than 5; as the raw material of copper, copper nitrate; and, as at least part of the raw material(s) of antimony, at least one antimony oxide in which the valency of antimony is larger than 0 but smaller than 5.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: April 14, 1998
    Assignee: Nippon Shokubai Co., Ltd.
    Inventors: Michio Tanimoto, Ichiro Mihara, Tatsuya Kawajiri
  • Patent number: 5556670
    Abstract: A flexible liquid crystal display panel includes spacers and cross members which are prevented from moving and from exfoliating, respectively, even when a force is applied thereto. In this panel, upper and lower substrates have flexibility, and spacers coated with an adhesive are fixed to orientation films formed on the substrates, by means of the adhesive. Thus, even when a force is applied from the outside, the spacers are prevented from moving, and therefore the distance between the substrates can be kept constant and the display characteristics of the liquid crystal can be made uniform. Further, a sealing member interposed between the substrates has holes through which cross members are fitted. This means that the cross members are reinforced by the sealing member, and hence they can be prevented from exfoliating from the substrates, keeping good electrical connection.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: September 17, 1996
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ichiro Mihara, Minoru Kumagai, Kunpei Kobayashi