Patents by Inventor Ichiro Omura

Ichiro Omura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840365
    Abstract: It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: November 17, 2020
    Assignees: Kyushu Institute of Technology, Mitsubishi Electric Corporation, Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Katsumi Satoh, Tomoko Matsudai
  • Publication number: 20200098902
    Abstract: It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.
    Type: Application
    Filed: December 9, 2017
    Publication date: March 26, 2020
    Inventors: Ichiro OMURA, Katsumi SATOH, Tomoko MATSUDAI
  • Patent number: 10411111
    Abstract: A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth DT, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 10, 2019
    Assignee: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Ichiro Omura, Masahiro Tanaka, Masanori Tsukuda, Yamato Miki
  • Publication number: 20180145147
    Abstract: A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth DT, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Applicant: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Ichiro Omura, Masahiro Tanaka, Masanori Tsukuda, Yamato Miki
  • Publication number: 20150123165
    Abstract: A high-voltage insulated gate type power semiconductor device includes a low-concentration first conductivity type base layer; a plurality of trenches selectively formed with large intervals and narrow intervals provided alternately, in a front surface of the low-concentration first conductivity type base layer; a gate insulating film formed on a surface of each of the plurality of trenches; a gate electrode formed inside the gate insulating film; and a second conductivity type base layer selectively formed between the adjacent trenches sharing the narrow interval. The high-voltage insulated gate type power semiconductor device includes a high-concentration first conductivity type source layer selectively formed on a front surface of the second conductivity type base layer.
    Type: Application
    Filed: May 29, 2013
    Publication date: May 7, 2015
    Applicant: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Ichiro Omura, Masahiro Tanaka, Masanori Tsukuda, Yamato Miki
  • Patent number: 7915617
    Abstract: A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Ichiro Omura
  • Publication number: 20110042715
    Abstract: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.
    Type: Application
    Filed: November 2, 2010
    Publication date: February 24, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masanori Tsukuda, Ichiro Omura
  • Patent number: 7868397
    Abstract: In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: January 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Tsukuda, Ichiro Omura
  • Patent number: 7864021
    Abstract: An integrated circuit device includes: a main interconnect; and a coil located on one side of the main interconnect at a position fixed with respect to the main interconnect, the coil having a central axis extending in a direction crossing the extending direction of the main interconnect. An induction current detectable by the coil is generated due to a current flowing through the main interconnect.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Matsushita, Ichiro Omura
  • Patent number: 7838926
    Abstract: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Tsukuda, Ichiro Omura
  • Patent number: 7772641
    Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
  • Patent number: 7732837
    Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: June 8, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura
  • Patent number: 7723783
    Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type alternately arranged in a lateral direction on the first semiconductor layer of the first conductivity type; a third semiconductor region of the second conductivity type formed on the first semiconductor region; a fourth semiconductor region of the first conductivity type formed on a portion of the surface of the third semiconductor region; a control electrode provided via an first insulating film in a groove formed in contact with the fourth semiconductor region, the third semiconductor region, and the first semiconductor region; a first main electrode electrically connected to the first semiconductor layer; a second main electrode forming a junction with the third and fourth semiconductor region; and a fifth semiconductor region of the second conductivity type.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: May 25, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura
  • Patent number: 7652510
    Abstract: A semiconductor device comprises a driver provided for a semiconductor element having a control electrode to which a drive voltage is applied, the semiconductor element being switched between the conduction state and the non-conduction state based on the drive voltage, the driver operative to apply the drive voltage to the control electrode; a detector operative to supply a voltage detection signal oscillating at a certain frequency to the control electrode to detect a first voltage having a certain relation to a voltage applied to the semiconductor element; and a controller operative to control the detector based on the first voltage detected at the detector.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: January 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Izumi, Ichiro Omura
  • Patent number: 7633153
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: December 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Publication number: 20090206365
    Abstract: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.
    Type: Application
    Filed: February 10, 2009
    Publication date: August 20, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masanori Tsukuda, Ichiro Omura
  • Patent number: 7564107
    Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: July 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Hironori Yoshioka, Ichiro Omura, Wataru Saito
  • Patent number: RE46799
    Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wataru Saito, Ichiro Omura, Kozo Kinoshita
  • Patent number: RE47198
    Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
  • Patent number: RE47641
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa