Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.

Abstract: A power semiconductor device has a first main electrode formed along a surface of a substrate, a first semiconductor layer of first conductive type electrically connected to the first main electrode, a cyclic structure section which is formed on the first semiconductor layer and has second semiconductor layers of first conductive type and third semiconductor layers of second conductive type alternately and cyclically formed along the surface of the substrate, a fourth semiconductor layer of second conductive type selectively formed on a part of the second and third semiconductor layers, a fifth semiconductor layer of first conductive type selectively formed on the fourth semiconductor layer, a second main electrode contacted the fourth and fifth semiconductor layers, a control electrode disposed adjacent via a first insulating film on the second, fourth and fifth semiconductor layers, and a depletion layer blocking section which is formed outside of the cyclic structure section and prevents a depletion layer

Abstract: An integrated circuit device includes: a main interconnect; and a coil located on one side of the main interconnect at a position fixed with respect to the main interconnect, the coil having a central axis extending in a direction crossing the extending direction of the main interconnect. An induction current detectable by the coil is generated due to a current flowing through the main interconnect.

Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Abstract: In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.

Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Abstract: A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN (0?x?1); a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0?y?1, x<y) and formed on the first semiconductor layer; a second conductivity type third semiconductor layer represented by a composition formula AlxGa1-xN (0?x?1) and selectively formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; a source electrode electrically connected to the second semiconductor layer; and a drain electrode electrically connected to the second semiconductor layer. The distance between the drain electrode and the third semiconductor layer is longer than the distance between the source electrode and the third semiconductor layer.

Abstract: A semiconductor device comprises a driver provided for a semiconductor element having a control electrode to which a drive voltage is applied, the semiconductor element being switched between the conduction state and the non-conduction state based on the drive voltage, the driver operative to apply the drive voltage to the control electrode; a detector operative to supply a voltage detection signal oscillating at a certain frequency to the control electrode to detect a first voltage having a certain relation to a voltage applied to the semiconductor element; and a controller operative to control the detector based on the first voltage detected at the detector.

Abstract: First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to form a first pillar layer. Third semiconductor pillar layers of the first conduction type and fourth semiconductor pillar layers of the second conduction type are arranged on the first pillar layer laterally, periodically and alternately at a second period smaller than the first period to form a second pillar layer. A semiconductor base layer of the second conduction type is formed on a surface of the fourth semiconductor pillar layer. A semiconductor diffused layer of the first conduction type is formed on a surface of the semiconductor base layer.

Abstract: A gate driving circuit and method which increases the switching frequency by use of a switching control circuit which controls operations of a first, second, third, and fourth switches. The switching control circuit performs switching control of a power MOSFET when the MOSFET is to be turned on, so that a period exists when the first and fourth switches are simultaneously ON. The switching circuit also performs switching control when a MOSFET is to be turned off, so that a period exists when the second and third switches are simultaneously ON.

Abstract: A semiconductor device comprises a semiconductor portion including first semiconductor layers of a first conduction type and second semiconductor layers of a second conduction type alternately arranged on the surface of a semiconductor substrate to form a striped shape. A main region is formed to arrange a main cell in a well. A current sense cell is arranged in a sense well. A sense region is formed having the direction of the length in a direction that intersects the direction of alternate arrangement of the first semiconductor layers and the second semiconductor layers.

Abstract: A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the n-AlGaN layer 104. The source electrode 201 and the drain electrode 202 form an ohmic contact with the n-AlGaN layer 104. The gate electrode 203 forms a Schottky junction with the n-AlGaN layer 104.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction str

Abstract: A nitride semiconductor device according to one embodiment of the present invention includes: a non-doped first aluminum gallium nitride (AlxGa1-xN (0?x?1)) layer which is formed as a channel layer; a non-doped or n type second aluminum gallium nitride (AlyGa1-yN (0?y?1, x <y)) layer which is formed on the first aluminum gallium nitride layer as a barrier layer; an aluminum nitride (AlN) film which is formed on the second aluminum gallium nitride layer as a gate insulating film lower layer; an aluminum oxide (AL2O3) film which is formed on the aluminum nitride film as a gate insulating film upper layer; a source electrode and a drain electrode which are formed as first and second main electrodes to be electrically connected to the second aluminum gallium nitride layer, respectively; and a gate electrode which is formed on the aluminum oxide film as a control electrode.

Abstract: Disclosed is a power semiconductor device, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are alternately and laterally arranged on the first semiconductor layer and, a fourth semiconductor layer of the second conductivity type selectively formed in the surface regions of the second and third semiconductor layers, a fifth semiconductor layer of the first conductivity type selectively formed in the surface region of the fourth semiconductor layer, and a control electrode formed on the surfaces of the second, fourth and fifth semiconductor layers, in which a layer thickness ratio A is given by the expression: 0<A=t/(t+d)?0.72 where t is the thickness of the first semiconductor layer, and d is the thickness of the second semiconductor layer.

Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.