Patents by Inventor Igal Kushnir

Igal Kushnir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11237195
    Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Sarit Zur, Igal Kushnir, Gil Horovitz, Rotem Banin, Sergey Bershansky
  • Publication number: 20210391853
    Abstract: Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.
    Type: Application
    Filed: December 28, 2018
    Publication date: December 16, 2021
    Inventors: Benjamin Jann, Ashoke Ravi, Satwik Patnaik, Elan Banin, Ofir Degani, Nebil Tanzi, Brandon Davis, Igal Kushnir, Jonathan Jensen, Sidharth Dalmia, Peter Pawliuk
  • Publication number: 20210367629
    Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Alexandros Margomenos, Igal Kushnir, Elan Banin, Ofir Degani
  • Patent number: 11121731
    Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
  • Publication number: 20210265999
    Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.
    Type: Application
    Filed: August 5, 2019
    Publication date: August 26, 2021
    Inventors: Ofir DEGANI, Igal KUSHNIR, Elan BANIN, Rotem BANIN
  • Publication number: 20210203333
    Abstract: Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station. The digitally controlled oscillator circuit arrangement comprises input circuitry for obtaining a frequency setting signal, the frequency setting signal comprising a plurality of signal components, selection circuitry for selecting one signal component of the plurality of signal components of the frequency setting signal based on an oscillation signal of the digitally controlled oscillator circuit arrangement, signal generation circuitry for generating the oscillation signal based on the selected signal component of the frequency setting signal, and output circuitry for providing the oscillation signal.
    Type: Application
    Filed: August 27, 2020
    Publication date: July 1, 2021
    Inventors: Igal KUSHNIR, Evgeny SHUMAKER, Aryeh FARBER, Gil HOROVITZ
  • Publication number: 20210116871
    Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.
    Type: Application
    Filed: June 26, 2017
    Publication date: April 22, 2021
    Inventors: Sarit Zur, Igal Kushnir, Gil Horovitz, Rotem Banin, Sergey Bershansky
  • Patent number: 10944409
    Abstract: A phase-locked loop is provided. The phase-locked loop includes a first loop including a con-trolled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is configured to generate first signal indicative of a timing difference between a reference signal and the oscillation signal. Further, the phase-locked-loop includes a second loop configured to generate a second signal indicative of a timing error of the oscillation signal's cycle time, and to generate a correction signal based on the second signal. The phase-locked loop additionally includes a combiner configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventor: Igal Kushnir
  • Publication number: 20210067182
    Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: Ashoke Ravi, Jann Benjamin, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
  • Publication number: 20210050857
    Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.
    Type: Application
    Filed: October 9, 2020
    Publication date: February 18, 2021
    Inventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
  • Publication number: 20210038874
    Abstract: An applicator for use in tissue treatment, a method and a kit using the same. The applicator includes (i) a first chamber for holding whole blood, (ii) a second chamber for holding a coagulation initiator, and (iii) a dispensing element configured for concomitantly receiving, upon actuating the applicator, a volume of whole blood from said first chamber and a volume of coagulation initiator from said second chamber and dispensing the two together onto a tissue in need of treatment.
    Type: Application
    Filed: November 26, 2018
    Publication date: February 11, 2021
    Applicant: REDDRESS LTD.
    Inventors: Igal KUSHNIR, Alon KUSHNIR
  • Patent number: 10917051
    Abstract: Methods and architectures for closed loop digital pre-distortion (DPD) in a multi-stream phased array communication system include sampling outputs, from transmit antennas or dedicated analog detectors, of a plurality of RF power amplifiers operating in transmission of multi-stream transmission, correcting or normalizing the detected outputs, summing the outputs into a combined DPD feedback signal and selecting pre-distortion vectors to be used in altering the output of the PAs.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventor: Igal Kushnir
  • Publication number: 20200395916
    Abstract: An electrical device (100) that comprises at least one signal filter (104) comprising a plurality of mechanical resonators (106 108, 110) in a substrate (102) and at least one further mechanical resonator (112) in the substrate (102) configured to oscillate at a reference frequency of an oscillator signal. An electrical system (300) comprising an electrical oscillator (306) a transceiver (302) and an antenna (310), and an electrical device (100). A method (1300) for providing an electrical device (100).
    Type: Application
    Filed: December 29, 2017
    Publication date: December 17, 2020
    Inventors: Igal Kushnir, Harry Skinner, Bernhard Raaf, Sharon Malevsky, Gil Horovitz
  • Patent number: 10809669
    Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir
  • Patent number: 10804911
    Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
  • Publication number: 20200306094
    Abstract: Device, method and assembly for wound treatment. Specifically a wound dressing device; an assembly, e.g. a kit-of-parts, including the device as a component; and method of wound dressing and use wherein the device is a key component. The device includes a cavity defined by concave walls surrounded by lips for attachment to skin in fluid tight manner and a closure removably fixed to the lips and sealing the cavity. The assembly also includes, as another component a device for introducing blood into the cavity after it is fixed over a wound to permit the blood to clot over the wound within the cavity. In use, the clotting mold device is fixed on top of a wound, and blood is introduced into the mold space to permit the blood to clot within the mold space to form a blood clot over the wound.
    Type: Application
    Filed: September 17, 2018
    Publication date: October 1, 2020
    Applicant: REDDRESS LTD.
    Inventors: Alon KUSHNIR, Igal KUSHNIR
  • Publication number: 20200281775
    Abstract: Wound dressing assembly including (i) blood-clotting mold device having an enclosure defined between walls of a main body and a removable closure over an opening and configured for introduction of blood thereinto, and (ii) coagulation initiator in amount sufficient to coagulate blood introduced into the enclosure to form a blood clot. The formed blood clot is transferable onto a wound. Method for preparing a wound dressing by introducing a volume of blood into the enclosure of the blood-clotting mold device, maintaining the blood within the enclosure for time sufficient to permit clotting of the blood to obtain a blood clot; removing said the closure to open the enclosure; and extracting the blood clot from the enclosure. The formed blood clot may be used in a method for dressing a wound by fixation of the clot onto the wound.
    Type: Application
    Filed: September 17, 2018
    Publication date: September 10, 2020
    Applicant: REDDRESS LTD.
    Inventors: Alon KUSHNIR, Igal KUSHNIR
  • Publication number: 20200287557
    Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
  • Publication number: 20200241672
    Abstract: A device for detecting a touch input to a surface comprises at least one radar transmitter component configured to transmit electromagnetic radiation in a radio frequency spectrum. The device further comprises at least one radar receiver component configured to receive a portion of the electromagnetic radiation reflected by an object performing the touch input to the surface. The device further comprises a control module configured to receive information related to the portion of the electromagnetic radiation received by the at least one radar receiver component. The control module is further configured to detect the touch input to the surface based on the information related to the portion of the electromagnetic radiation received by the at least one radar receiver component.
    Type: Application
    Filed: August 24, 2017
    Publication date: July 30, 2020
    Inventors: Igal Kushnir, Ofir Degani
  • Publication number: 20200235744
    Abstract: A phase-locked loop is provided. The phase-locked loop includes a first loop including a con-trolled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is configured to generate first signal indicative of a timing difference between a reference signal and the oscillation signal. Further, the phase-locked-loop includes a second loop configured to generate a second signal indicative of a timing error of the oscillation signal's cycle time, and to generate a correction signal based on the second signal. The phase-locked loop additionally includes a combiner configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.
    Type: Application
    Filed: July 24, 2017
    Publication date: July 23, 2020
    Inventor: Igal KUSHNIR