Patents by Inventor Igor Arsovski

Igor Arsovski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200381355
    Abstract: A barrier or “crackstop” that is configured to conduct electrical signals. These configurations may form a wall around integrated, active circuitry of a semiconductor die. This wall may include a conductor that follows a three-dimensional pathway from one side to the other side of the wall. This pathway may have sections that overlap, or double-back, so that portions of the conductor overlap along their individual length. These sections prevent crack propagation internal to the wall.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Applicant: Avera Semiconductor LLC
    Inventors: Nicholas A. Polomoff, Igor Arsovski, Mark W. Kuemerle
  • Patent number: 10839931
    Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 17, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Igor Arsovski, Eric D. Hunt-Schroeder, Michael A. Ziegerhofer
  • Publication number: 20200334014
    Abstract: An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ranjan B. LOKAPPA, Igor ARSOVSKI
  • Publication number: 20200321070
    Abstract: The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 8, 2020
    Inventors: Deepak I. HANAGANDI, Igor ARSOVSKI, Michael A. ZIEGERHOFER, Valerie H. CHICKANOSKY, Kalpesh R. LODHA
  • Patent number: 10795430
    Abstract: A semiconductor device is disclosed that includes, among other things, a computing device including a plurality of transistors, an activity monitor to determine an activity metric associated with the plurality of transistors, and a power controller to, responsive to the activity metric indicating a first activity level, set a power supply voltage for the plurality of transistors to a first value, and responsive to the activity metric indicating a second activity level less than the first activity level, set the power supply voltage to a second value greater than the first value and apply a first reverse back bias voltage to the plurality of transistors to increase a threshold voltage of the plurality of transistors.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Igor Arsovski, Kushal Kamal
  • Patent number: 10796750
    Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Akhilesh Patil, Eric D. Hunt-Schroeder
  • Patent number: 10748635
    Abstract: The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 18, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Igor Arsovski, Kyle M. Holmes
  • Publication number: 20200243130
    Abstract: The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N?1 of the consecutive read operations, and N is an integer number of the consecutive read operations.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 30, 2020
    Inventors: Igor ARSOVSKI, Akhilesh PATIL, Eric D. HUNT-SCHROEDER
  • Patent number: 10705797
    Abstract: Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry bit generation circuit has different sections, which process different sequential sets of bit pairs and which have different sparsity configurations. As a result, generation of the primary carry bits is non-uniform. That is, in the different sections the primary carry bits are generated at different carry bit-to-bit pair ratios (e.g., the carry bit-to-bit pair ratios for the different sections can be 1:2, 1:4, and 1:2, respectively). For optimal performance, the specific bit pairs for which these primary carry bits are generated varies depending upon whether the maximum operand size is an odd number of bits or an even number.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 7, 2020
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Ranjan B. Lokappa, Igor Arsovski
  • Publication number: 20200167127
    Abstract: Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry bit generation circuit has different sections, which process different sequential sets of bit pairs and which have different sparsity configurations. As a result, generation of the primary carry bits is non-uniform. That is, in the different sections the primary carry bits are generated at different carry bit-to-bit pair ratios (e.g., the carry bit-to-bit pair ratios for the different sections can be 1:2, 1:4, and 1:2, respectively). For optimal performance, the specific bit pairs for which these primary carry bits are generated varies depending upon whether the maximum operand size is an odd number of bits or an even number.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ranjan B. Lokappa, Igor Arsovski
  • Publication number: 20200152270
    Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Igor ARSOVSKI, Suparna BHATTACHARYA, Arvind KUMAR
  • Publication number: 20200072902
    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Igor ARSOVSKI, John R. GOSS, Eric D. HUNT-SCHROEDER, Andrew K. KILLORIN
  • Patent number: 10566058
    Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, Suparna Bhattacharya, Arvind Kumar
  • Patent number: 10551436
    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin
  • Publication number: 20200020388
    Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 16, 2020
    Inventors: Igor Arsovski, Akhilesh Patil, Eric D. Hunt-Schroeder
  • Patent number: 10489455
    Abstract: A scoped search engine is disclosed. The scoped search engine includes a memory unit storing reference data records. The scoped search engine also includes a data comparison unit that searches the reference data records using different searches. The scoped search engine further includes a match analysis unit that combines result data from the different searches and determines a scope for a subsequent search based on the combined result data.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Samuel S. Adams, Igor Arsovski, Suparna Bhattacharya, John M. Cohn, Gary P. Noble, Krishnan S. Rengarajan
  • Publication number: 20190348137
    Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Igor ARSOVSKI, Eric D. HUNT-SCHROEDER, Michael A. ZIEGERHOFER
  • Patent number: 10446233
    Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Qing Li, Xiaoli Hu, Wei Zhao, Jieyao Liu
  • Patent number: 10438678
    Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Eric D. Hunt-Schroeder, Michael A. Ziegerhofer
  • Publication number: 20190295676
    Abstract: The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.
    Type: Application
    Filed: March 22, 2018
    Publication date: September 26, 2019
    Inventors: Igor ARSOVSKI, Kyle M. HOLMES