Abstract: A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.

Abstract: A scoped search engine is disclosed. The scoped search engine includes a memory unit storing reference data records. The scoped search engine also includes a data comparison unit that searches the reference data records using different searches. The scoped search engine further includes a match analysis unit that combines result data from the different searches and determines a scope for a subsequent search based on the combined result data.

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure.

Abstract: Approaches for an integrated circuit ternary content addressable memory (TCAM) are provided. A system includes an array of XY TCAM cells and respective translation circuits connected to respective pairs of the XY TCAM cells. The system also includes a memory controller structured to provide control signals to the respective translation circuits. The memory controller and respective translation circuits are structured to control the array of XY TCAM cells to perform single cycle update and single cycle search operations.

Abstract: Disclosed are single-ended sensing circuits. Each of the sensing circuits comprises at least a sense amplifier connected to a sense node, an isolation field effect transistor (FET) connected in series between the sense node and a signal line node, and a pre-charged device connected to the sense node. In order to achieve a relatively fast pre-charge of both the sense and signal line nodes and to also achieve a relatively fast and accurate sense of the sense node, the single-ended circuits further incorporate a variable reference voltage generator connected to the gate of the isolation FET for selectively applying different reference voltages to the gate during pre-charging and sensing operations, respectively, and/or a second pre-charge device connected to the signal line node for facilitating pre-charging of that signal line node.

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract: A content addressable memory (CAM) search engine is disclosed. The CAM search engine includes a data compare plane having a content addressable memory die including an array of comparison cells. The CAM search engine further includes a memory stack on the data compare plane. The memory stack has stacked memory dies including memory banks. The array of comparison cells includes parallel interconnects. The parallel interconnects electrically connect to outputs of the memory banks. The comparison cells are time-shared among the one or more memory banks.

Abstract: A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.

Abstract: A circuit is provided for that includes one or more TCAM arrays including one or more matchlines configured to model a neural network. Each of the one or more TCAM arrays models a connected group of neurons such that input search data into the one or more matchlines is modeled as neuron dendrite information, and the output from the one or more matchlines is modeled as neuron axon information. The circuit further includes one or more additional bits included within each of the one or more matchlines that are configured to model connectivity strength between each neuron dendrite and axon. The circuit also includes a real-time learning block included within each of the one or more TCAM arrays configured to modify the connectivity strength between each neuron dendrite and axon using wild-cards written and stored in the one or more additional bits.

Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.

Abstract: A content addressable memory (CAM) search engine is disclosed. The CAM search engine includes a data compare plane having a content addressable memory die including an array of comparison cells. The CAM search engine further includes a memory stack on the data compare plane. The memory stack has stacked memory dies including memory banks. The array of comparison cells includes parallel interconnects. The parallel interconnects electrically connect to outputs of the memory banks.

Abstract: A content-addressable memory (CAM) with computational capability is described. The CAM includes an array of CAM cells arranged in rows and columns with a pair of search lines associated with each column of the array and a match line associated with each row of the array. The array of CAM cells is configured to implement, for a given cycle, either a read operation of data contained in a single selected column, or one of a plurality of different bitwise logical operations on data contained in multiple selected columns. All of the pairs of search lines in the columns of the array are configured to a certain state to implement the read operation or one of the plurality of different bitwise logical operations. A result of the read operation or one of the plurality of different bitwise logical operations is outputted onto all of the match lines in the array.

Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.

Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

Abstract: A circuit is provided for that includes one or more TCAM arrays including one or more matchlines configured to model a neural network. Each of the one or more TCAM arrays models a connected group of neurons such that input search data into the one or more matchlines is modeled as neuron dendrite information, and the output from the one or more matchlines is modeled as neuron axon information. The circuit further includes one or more additional bits included within each of the one or more matchlines that are configured to model connectivity strength between each neuron dendrite and axon. The circuit also includes a real-time learning block included within each of the one or more TCAM arrays configured to modify the connectivity strength between each neuron dendrite and axon using wild-cards written and stored in the one or more additional bits.

Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

Abstract: Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.

Abstract: An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically conductive medium and a second switch adapted to couple a ground supply voltage to the conductive medium. A first biasing network includes a first input that is coupled to the conductive medium, a second input that receives a clock signal, and a first output that is adapted to couple a second positive supply voltage to each input of the first and the second switch. Based on the second switch coupling the conductive medium to the ground supply voltage and the received clock signal generating a logic low, the biasing network reverse biases the first switch by coupling the second positive supply voltage to the respective input of the first switch causing a leakage current reduction in the first switch.

Abstract: Approaches for an integrated circuit ternary content addressable memory (TCAM) are provided. A system includes an array of XY TCAM cells and respective translation circuits connected to respective pairs of the XY TCAM cells. The system also includes a memory controller structured to provide control signals to the respective translation circuits. The memory controller and respective translation circuits are structured to control the array of XY TCAM cells to perform single cycle update and single cycle search operations.

Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.