Abstract: A solid-state image pickup device is provided in which a pixel forming region 4 and a peripheral circuit forming region 20 are formed on the same semiconductor substrate, a first element isolation portion is formed by an element isolation layer 21 in which an insulating layer is buried into a semiconductor substrate 10 in the peripheral circuit forming region 20, a second element isolation portion is composed of an element isolation region 11 formed within the semiconductor substrate 10 and an element isolation layer 12 projected in the upper direction from the semiconductor substrate 10 in the pixel forming region 4 and an element isolation layer 21 of the first element isolation portion and the element isolation layer 12 of the second element isolation portion contain the same insulating layers 17, 18 and 19. This solid-state image pickup device has a structure capable of suppressing a noise relative to a pixel signal and which can be microminiaturized in the peripheral circuit forming region.

Abstract: A solid-state image pickup device is provided in which a pixel forming region 4 and a peripheral circuit forming region 20 are formed on the same semiconductor substrate, a first element isolation portion is formed by an element isolation layer 21 in which an insulating layer is buried into a semiconductor substrate 10 in the peripheral circuit forming region 20, a second element isolation portion is composed of an element isolation region 11 formed within the semiconductor substrate 10 and an element isolation layer 12 projected in the upper direction from the semiconductor substrate 10 in the pixel forming region 4 and an element isolation layer 21 of the first element isolation portion and the element isolation layer 12 of the second element isolation portion contain the same insulating layers 17, 18 and 19. This solid-state image pickup device has a structure capable of suppressing a noise relative to a pixel signal and which can be microminiaturized in the peripheral circuit forming region.

Abstract: A solid-state image pickup device is provided in which a pixel forming region 4 and a peripheral circuit forming region 20 are formed on the same semiconductor substrate, a first element isolation portion is formed by an element isolation layer 21 in which an insulating layer is buried into a semiconductor substrate 10 in the peripheral circuit forming region 20, a second element isolation portion is composed of an element isolation region 11 formed within the semiconductor substrate 10 and an element isolation layer 12 projected in the upper direction from the semiconductor substrate 10 in the pixel forming region 4 and an element isolation layer 21 of the first element isolation portion and the element isolation layer 12 of the second element isolation portion contain the same insulating layers 17, 18 and 19. This solid-state image pickup device has a structure capable of suppressing a noise relative to a pixel signal and which can be microminiaturized in the peripheral circuit forming region.

Abstract: A solid-state imaging device with a semiconductor substrate; a pixel formation region in the substrate and including a pixel made of a photoelectric conversion element; and an element isolation portion in the substrate and including an element isolation insulating layer and an impurity element isolation region. The element isolation insulating layer is positioned in a surface of the substrate. The impurity element isolation region is positioned under the element isolation insulating layer and within the substrate. The impurity element isolation region has at least a portion with a width that is narrower than that of the element isolation insulating layer. The photoelectric conversion element extends to a position under the element isolation insulating layer of the element isolation portion.

Abstract: A semiconductor image sensor module and a method for manufacturing thereof as well as a camera and a method for manufacturing thereof are provided in which a semiconductor image sensor chip and an image signal processing chip are connected with a minimum parasitic resistance and parasitic capacity and efficient heat dissipation of the image signal processing chip and shielding of light are simultaneously obtained.

Abstract: A solid-state imaging device is provided in which noise to an image signal is restrained and miniaturization is facilitated in a peripheral circuit formation region. A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried in a semiconductor substrate 10; in the pixel formation region 4 a second element isolation portion made of an element isolation region 11 formed inside the semiconductor substrate 10 and an element isolation layer 12 projecting upward from the semiconductor substrate 10 is formed; and a photoelectric conversion element 16 (14, 15) is formed extending to a position under the element isolation layer 12 of the second element isolation portion.

Abstract: A semiconductor image sensor module and a method for manufacturing thereof as well as a camera and a method for manufacturing thereof are provided in which a semiconductor image sensor chip and an image signal processing chip are connected with a minimum parasitic resistance and parasitic capacity and efficient heat dissipation of the image signal processing chip and shielding of light are simultaneously obtained.

Abstract: A solid-state imaging device is provided in which noise to an image signal is restrained and miniaturization is facilitated in a peripheral circuit formation region. A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried in a semiconductor substrate 10; in the pixel formation region 4 a second element isolation portion made of an element isolation region 11 formed inside the semiconductor substrate 10 and an element isolation layer 12 projecting upward from the semiconductor substrate 10 is formed; and a photoelectric conversion element 16 (14, 15) is formed extending to a position under the element isolation layer 12 of the second element isolation portion.

Abstract: A solid-state imaging device is provided in which noise to an image signal is restrained and miniaturization is facilitated in a peripheral circuit formation region. A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried in a semiconductor substrate 10; in the pixel formation region 4 a second element isolation portion made of an element isolation region 11 formed inside the semiconductor substrate 10 and an element isolation layer 12 projecting upward from the semiconductor substrate 10 is formed; and a photoelectric conversion element 16 (14, 15) is formed extending to a position under the element isolation layer 12 of the second element isolation portion.

Abstract: A semiconductor image sensor module and a method for manufacturing thereof as well as a camera and a method for manufacturing thereof are provided in which a semiconductor image sensor chip and an image signal processing chip are connected with a minimum parasitic resistance and parasitic capacity and efficient heat dissipation of the image signal processing chip and shielding of light are simultaneously obtained.

Abstract: The present invention provides a solid-state imaging device having an array of unit pixels, each unit pixel including a photoelectric conversion element and an amplifier transistor for amplifying a signal corresponding to charge obtained by photoelectric conversion through the photoelectric conversion element and outputting the resultant signal. The amplifier transistor includes a buried channel MOS transistor. According to the present invention, 1/f noise can be basically reduced.

Abstract: Problems in reliability and cross-talk of MRAM, which are intrinsically ascribable to the structure thereof, are solved at the same time.

Abstract: A solid-state image pickup device is provided in which a pixel forming region 4 and a peripheral circuit forming region 20 are formed on the same semiconductor substrate, a first element isolation portion is formed by an element isolation layer 21 in which an insulating layer is buried into a semiconductor substrate 10 in the peripheral circuit forming region 20, a second element isolation portion is composed of an element isolation region 11 formed within the semiconductor substrate 10 and an element isolation layer 12 projected in the upper direction from the semiconductor substrate 10 in the pixel forming region 4 and an element isolation layer 21 of the first element isolation portion and the element isolation layer 12 of the second element isolation portion contain the same insulating layers 17, 18 and 19. This solid-state image pickup device has a structure capable of suppressing a noise relative to a pixel signal and which can be microminiaturized in the peripheral circuit forming region.

Abstract: A solid-state imaging device is provided in which noise to an image signal is restrained and miniaturization is facilitated in a peripheral circuit formation region. A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried in a semiconductor substrate 10; in the pixel formation region 4 a second element isolation portion made of an element isolation region 11 formed inside the semiconductor substrate 10 and an element isolation layer 12 projecting upward from the semiconductor substrate 10 is formed; and a photoelectric conversion element 16 (14, 15) is formed extending to a position under the element isolation layer 12 of the second element isolation portion.

Abstract: Problems in reliability and cross-talk of MRAM, which are intrinsically ascribable to the structure thereof, are solved at the same time.

Abstract: Problems in reliability and cross-talk of MRAM, which are intrinsically ascribable to the structure thereof, are solved at the same time.

Abstract: In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.

Abstract: In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.