Abstract: A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.

Abstract: In a BiMOS semiconductor device, emitter and base electrodes formed by polycrystalline Si of a bipolar transistor are isolated from each other by way of a sidewall and an insulator layer. As this insulator layer acts as an offset during the formation of the sidewall, its layer thickness can be made larger. Further, as this insulator layer is not provided in a MOS region, its step can be made smaller. Consequently, parasitic capacitance can be reduced while the insulator layer can be made thicker. Thus, there can be achieved both fast operation and high reliability of the bipolar transistor and, moreover, reduction in the reliability of a MOS transistor can also be prevented.

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e.

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: A pair of load transistors of a flip-flop circuit constituting a memory cell consist of thin film transistors, and channel regions of the pair of load transistors overlap drain regions of the transistors through a gate insulating film. For this reason, a channel length of the load transistor can be sufficiently increased, and a leakage current of the load transistor can be reduced.

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: A pair of load transistors of a flip-flop circuit constituting a memory cell consist of thin film transistors, and channel regions of the pair of load transistors overlap drain regions of the transistors through a gate insulating film. For this reason, a channel length of the load transistor can be sufficiently increased, and a leakage current of the load transistor can be reduced.

Abstract: In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e.

Abstract: A parallel computer has an operation request function and a plurality of processor elements. Each processor element has a sharable distributed memory for holding data, and is interconnected to a network to permit communication. Each processor element comprises a request sent unit for sending an operation request message for causing another processor element connected to a memory module to execute a recursive defining operation. The memory module stores data to be recursively defined. Each processor element further comprises an operation request execution element for accepting a message from another processor, temporarily stopping any other operation of the processor element in accordance with the content of the message, and executing the requested operation. Registers are also used for executing the operation requested by the other processor in addition to the general purpose registers and floating point registers.

Abstract: A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data.

Abstract: In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

Abstract: In an analysis processor which utilizes a parameter table for setting a processing condition and analyzes data in accordance with the content of table, a process for registering/correcting the parameter table is standarized for various analysis processing programs so that each of the analysis processing programs is divided into an analysis processing procedure instruction section and a parameter table section. Thus, a plurality of different analysis process can be performed in one analysis processor. Any table in the analysis processing programs may be readily referred to by an instruction through a keyboard of the analysis processor and may be registered and corrected. Thus, a user can alter the analysis processing program as he/she desires.