Patents by Inventor Ikuro Masuda

Ikuro Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4661723
    Abstract: A novel composite circuit comprises a first bipolar transistor with a collector of a first conductivity type connected to a first potential, an emitter of the first conductivity type connected to an output, a second bipolar transistor with a collector of the first conductivity type connected to the output and an emitter of the first conductivity type connected to a second potential, a field effect transistor of a second conductivity type with a gate connected to an input, a source connected to a third potential and a drain connected to the base of the first bipolar transistor, a field effect transistor of the first conductivity type with a gate connected to the input, a drain connected to the base of the first bipolar transistor, and a source connected to the base of the second bipolar transistor, and a unidirectional element inserted between the output and the drain of the field effect transistor of the first conductivity type and having a direction of rectification opposite to that of the PN junction formed
    Type: Grant
    Filed: July 23, 1984
    Date of Patent: April 28, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Masahiro Iwamura, Motohisa Nishihara
  • Patent number: 4617648
    Abstract: A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, is disclosed. The device includes: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with the flip-flop circuit, when the device is diagnosed to detect a fault therein; second means connected to the output side of the flip-flop circuit for making and breaking the closed loop of the gates in accordance with the first write timing signal; third means connected to the output side of the flip-flop circuit for supplying the diagnostic data to the flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of the flip-flop circuit for blocking a signal applied to the input side of the flip-flop circuit, in accordance with the diagnosis control signal.
    Type: Grant
    Filed: November 8, 1984
    Date of Patent: October 14, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Kuboki, Hideo Maejima, Ikuro Masuda
  • Patent number: 4613970
    Abstract: A method of diagnosing an integrated circuit device having a plurality of combinational circuits, at least one input memory circuit connected to an input side of the combinational circuits, and an output memory circuit connected to an output side of the combinational circuits is disclosed. An input diagnostic signal is selectively applied to at least one input memory circuit connected to a given one of the combinational circuits, to read out a diagnostic signal stored in an output memory circuit connected to the given combinational circuit. Further, an integrated circuit device is disclosed which is suited to be diagnosed in the above method.
    Type: Grant
    Filed: January 31, 1984
    Date of Patent: September 23, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Hideo Maejima, Terumine Hayashi, Kazumi Hatayama
  • Patent number: 4589007
    Abstract: A semiconductor integrated circuit device is disclosed. A plurality of unit cells, each having at least a basic transistor device formed on one main surface of a semiconductor substrate, are arranged in a line to form a unit cell line. At least two of such unit cell lines are arranged adjacent to and in parallel with each other to form a basic cell line. A plurality of such basic cell lines are arranged in parallel with each other with a wiring region of a predetermined width being interleaved between adjacent basic cell lines.
    Type: Grant
    Filed: September 6, 1983
    Date of Patent: May 13, 1986
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Shigeo Kuboki, Mitsuhiro Ikeda, Akihiko Takano, Yoji Nishio, Ikuro Masuda
  • Patent number: 4523276
    Abstract: An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are stored in another memory in the form of data of the fixed word length. The data stored in another memory are subjected to data organization to be outputted in the form of data of a given word length. Each of the memories is divided into a plurality of regions, and each region stores therein data of the same word length, respectively.
    Type: Grant
    Filed: September 19, 1983
    Date of Patent: June 11, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Maejima, Ikuro Masuda, Hidekazu Matsumoto, Shyoichi Miyazawa
  • Patent number: 4500951
    Abstract: In a plant control system, a transmission channel includes loop transmission lines arranged in duplex. Equivalently connected to this transmission channel are a plurality of one-loop controller stations, a backup station backing up a disabled one of the plural controller stations and a display station for displaying the status of the controller stations and the backup station. Each of the controller stations, backup station and display station includes a built-in microcomputer. Each of these stations includes also a transmission interface circuit and a self-diagnostic circuit. The transmission interface circuit in each station selects one of the transmission lines for data transmission between its own station and the others. The self-diagnostic circuit in each station detects the presence of failure of normal operation of its own station and disconnects the disabled station from the transmission line, so that the other stations may not be adversely affected by the disabled station.
    Type: Grant
    Filed: December 30, 1981
    Date of Patent: February 19, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Norihiko Sugimoto, Nobuhiro Hamada, Ikuro Masuda, Jinichi Sakurai
  • Patent number: 4366478
    Abstract: Disclosed is a signal transmitting and receiving apparatus for transmitting and receiving parallel-by-word data signals, converting the parallel-by-word data signal to serial-by-word data signal, and transmitting the serial-by-word data signal to control units connected in a multi-drop connection configuration or receiving the signals transmitted from the control units.An external control mode and an internal control mode in receiving the parallel-by-word data signal, a simulation mode, and the prevention of competing status between a write timing of the parallel-by-word data to a buffer memory and a read timing of the data for converting it to serial-by-word data are described.
    Type: Grant
    Filed: January 5, 1981
    Date of Patent: December 28, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Hisayoshi Shiraishi, Seiichiro Ogawa, Shigeo Shiono, Jinichi Sakurai, Takeo Yuminaka
  • Patent number: 4200225
    Abstract: A diagnostic check system for a digital signal circuit, in which, in a state where a plurality of digital signals are being sent out from a processor such as a microcomputer through an interface and photo-coupling elements to a controlled apparatus, the processor periodically processes all the digital signals to simultaneously cause them to be the same signal mode "1" or "0" for a period of time that is too short for the controlled apparatus to respond to the change in the levels of the digital signals, and the processor also detects whether the modes of all the signals transferred from the photo-coupling elements to the controlled apparatus for the short period of time are coincident or not.
    Type: Grant
    Filed: June 5, 1978
    Date of Patent: April 29, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Ueno, Ikuro Masuda
  • Patent number: 3967242
    Abstract: An automatic working machine adapted to carry out works such as cutting, filling, tightening and loosening, which comprises a visual unit for detecting, by means of the image information, a plurality of works and obstacles existing on an object, a working unit which works against a particular work and moves in relation to the object, and a tactile sensor provided in the vicinity of the working unit, the working unit being precisely positioned by the aid of the tactile sensor when the visual unit detects the particular work, the relative position being maintained during the operation, and the working unit along with the tactile sensor being retracted when the visual unit detects an obstacle, to avoid collision thereof with the obstacle.
    Type: Grant
    Filed: June 13, 1974
    Date of Patent: June 29, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Isoo, Shinji Matsuoka, Shigeru Matsuoka, Takeshi Uno, Sadahiro Ikeda, Ikuro Masuda, Koji Kurokawa