Patents by Inventor IMEC

IMEC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130161588
    Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 27, 2013
    Applicants: Katholieke Universiteit Leuven, K.U.LEUVEN R&D, IMEC
    Inventors: IMEC, Katholieke Universiteit Leuven, K.U.LEUVEN R&D
  • Publication number: 20130166616
    Abstract: The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 27, 2013
    Applicants: IMEC, SAMSUNG ELECTRONICS CO. LTD., KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D
    Inventors: IMEC, KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D, SAMSUNG ELECTRONICS CO. LTD.
  • Publication number: 20130161583
    Abstract: The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 27, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130153923
    Abstract: Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 20, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130155572
    Abstract: A method for manufacturing a metal-insulator-metal (MIM) stack is described. The method includes forming a temporary stack by depositing a bottom electrode comprising at least one metal layer; depositing a dielectric comprising at least one layer of a dielectric material having a first dielectric constant value; and depositing a top electrode comprising at least one metal layer. The step of depositing the bottom and/or top electrode includes depositing a non-conductive metal oxide layer directly in contact with the dielectric; and after the step of depositing the bottom and/or top electrode's non-conductive metal oxide layer and the dielectric, subjecting the temporary stack to a stimulus, which transforms the non-conductive metal oxide into a thermodynamically stable oxide having conductive properties or into a metal, and the dielectric material into a crystalline form having a second dielectric constant value higher than the first dielectric constant value, thereby creating the final MIM stack.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 20, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130155409
    Abstract: A method and system for optically determining a substantially fully activated doping profile are disclosed. The substantially fully activated doping profile is characterized by a set of physical parameters. In one aspect, the method includes obtaining a sample comprising a fully activated doping profile and a reference, and obtaining photomodulated reflectance (PMOR) offset curve measurement data and DC reflectance measurement data for the sample including the fully activated doping profile and for the reference. The method also includes determining values for the set of physical parameters of the doping profile based on both the photomodulated reflectance offset curve measurements and the DC reflectance measurements.
    Type: Application
    Filed: November 29, 2012
    Publication date: June 20, 2013
    Applicants: Katholieke Universiteit Leuven, IMEC
    Inventors: IMEC, Katholieke Universiteit Leuven
  • Publication number: 20130154112
    Abstract: The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 20, 2013
    Applicants: KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D, IMEC
    Inventors: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
  • Publication number: 20130143501
    Abstract: A communication device is disclosed. The device may be in particular a radio transmitter and a receiver that can operate with low power consumption and with improved interference rejection, therefore particularly suitable for use in low-power communication systems, such as wireless sensor networks and wireless body area networks. In one aspect, multiple frequency tones (carriers) are used to carry information from the transmitter, such that a RF signal having multiple radio frequency components is produced and transmitted. In the receiver, an envelope detector is still the RF down-converter. After down-converting intermodulation components are extracted containing amplitude, phase and frequency information of the multiple radio frequency components. This allows the desired signal (the baseband information) to be distinguished from the carriers and unwanted interference.
    Type: Application
    Filed: November 16, 2012
    Publication date: June 6, 2013
    Applicant: Stichting IMEC Nederland
    Inventor: Stichting IMEC Nederland
  • Publication number: 20130134382
    Abstract: The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 30, 2013
    Applicants: KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D, IMEC
    Inventors: IMEC, Katholieke Universiteit Leuven, K.U. LEUVEN R&D
  • Publication number: 20130134436
    Abstract: A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 30, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130132529
    Abstract: A method for determining a data format for processing data to be transmitted along a communication path is disclosed. In one aspect, the method includes identifying at run-time an operational configuration based on received information on the conditions for communication on the communication path. The method may also include selecting according to the identified operational configuration, a data format for processing data to be transmitted among a plurality of predetermined data formats.
    Type: Application
    Filed: October 11, 2012
    Publication date: May 23, 2013
    Applicant: IIMEC
    Inventor: IMEC
  • Publication number: 20130130180
    Abstract: A method for producing a GaNLED device, wherein a stack of layers comprising at least a GaN layer is texturized, is disclosed. The method involves (i) providing a substrate comprising on its surface said stack of layers, (ii) depositing a resist layer directly on said stack, (iii) positioning a mask above said resist layer, said mask covering one or more first portions of said resist layer and not covering one or more second portions of said resist layer, (iv) exposing said second portions of said resist layer to a light source, (v) removing the mask, and (vi) bringing the resist layer in contact with a developer comprising potassium, wherein said developer removes said resist portions that have been exposed and texturizes the surface of at least the top layer of said stack by wet etching said surface, in the areas situated underneath said resist portions that have been exposed.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 23, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130119014
    Abstract: A method for treating a surface of a porous material in an environment is provided, comprising setting the temperature of the surface to a value T1 and setting the pressure of the environment to a value P1, contacting the surface with a fluid having a solidifying temperature at the pressure value P1 above the value T1 and having a vaporizing temperature at the pressure value P1 below 80° C., thereby solidifying the fluid in pores of the material, thereby sealing the pores, treating the surface, wherein the treatment is preferably an etching or a modification of the surface, and setting the temperature of the surface to a value T2 and setting the pressure of the environment to a value P2 in such a way as to vaporize the fluid.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 16, 2013
    Applicants: GLOBALFOUNDERIES Inc., IMEC
    Inventors: IMEC, GLOBALFOUNDERIES Inc.
  • Publication number: 20130116577
    Abstract: A system for the analysis of ECG signals is disclosed. The system may comprise (i) at least one readout channel, configured to receive an analogue ECG signal acquired from at least one electrode attached to a body, and to extract an analogue measured ECG signal and analogue electrode-skin impedance signals; (ii) at least one ADC, configured to convert those extracted analogue signals at the readout channel into digital signals; (iii) a digital adaptive filter unit, configured to calculate a digital motion artifact estimate based on said digital versions of the measured ECG signal and the electrode-skin impedance signals; (iv) at least one DAC, configured to convert said digital motion artifact estimate into an analogue signal; and (v) a feedback loop for sending said analogue motion artifact estimate signal back to the readout channel configured to deduct said analogue motion artifact estimate signal from said analogue measured ECG signal.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 9, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130116588
    Abstract: A microprocessor configured to receive and process digitized signals derived from an analogue ECG signal is provided. An example microprocessor comprises a beat detection unit configured to receive the in-phase and quadrature phase band power signals, calculate a band power value and an adaptive threshold value, and compare said band power value with said adaptive threshold value to detect a QRS complex of the ECG signal indicative of a detected valid beat; and an R peak detection unit configured to receive the digital ECG signal and information about the detected valid beat, select a portion of the received ECG signal as a first time window around the detected valid beat; determine the location of a first R peak position; and perform a time domain search in a second time window around said first R peak position in order to refine the location of an R peak position.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 9, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130113549
    Abstract: A variable capacitor circuit is disclosed. The variable capacitor circuit includes a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which the equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 9, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130111977
    Abstract: The application describes methods and apparatus for chemical sensing, e.g. gas sensing, which have high sensitivity but low power operation. A sensor is described having a flexible membrane comprising a III/N heterojunction structure configured so as to form a two dimensional electron gas within said structure. A sensing material is disposed on at least part of the flexible membrane, the sensing material being sensitive to one or more target chemicals so as to undergo a change in physical properties in the presence of said one or more target chemicals. The sensing material is coupled to said heterojunction structure such that said change in physical properties of the sensing material imparts a change in stress within the heterojunction structure which modulates the resistivity of the two dimensional electron gas.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 9, 2013
    Applicant: Stichting IMEC Nederland
    Inventor: Stichting IMEC Nederland
  • Publication number: 20130102140
    Abstract: A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 25, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130100577
    Abstract: A method for forming a Metal-Insulator-Metal Capacitor (MIMCAP) structure and the MIMCAP structure thereof are described. An example electronic device includes a first electrode, and a layer of a dielectric material including titanium oxide and a first dopant ion. The layer of the dielectric material is formed on the first electrode. The first dopant ion has a size mismatch of 10% or lower compared to the Ti4+ ion and the dielectric material has a rutile tetragonal crystalline structure at temperatures below 650° C. The example electronic device further includes a second electrode, formed upon the dielectric material layer.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 25, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130102121
    Abstract: A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 25, 2013
    Applicant: IMEC
    Inventor: IMEC