Patents by Inventor IMEC

IMEC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130084700
    Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 4, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Publication number: 20130075876
    Abstract: A method for at least partially sealing a porous material is provided, comprising forming a sealing layer onto the porous material by applying a sealing compound comprising oligomers wherein the oligomers are formed by ageing a precursor solution comprising cyclic carbon bridged organosilica and/or bridged organosilanes. The method is especially designed for low k dielectric porous materials to be incorporated into semiconductor devices.
    Type: Application
    Filed: September 18, 2012
    Publication date: March 28, 2013
    Applicants: Universiteit Gent, IMEC
    Inventors: IMEC, Universiteit Gent
  • Publication number: 20130078155
    Abstract: A micro-fluidic device is described. The micro-fluidic device includes a semiconductor substrate; at least one micro-reactor in the semiconductor substrate; one or more micro-fluidic channels in the semiconductor substrate, connected to the at least one micro-reactor; a cover layer bonded to the semiconductor substrate for sealing the one or more micro-fluidic channels; and at least one through-substrate trench surrounding the at least one micro-reactor and the one or more micro-fluidic channels.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 28, 2013
    Applicants: IMEC, PANASONIC, KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D
    Inventors: IMEC, Katholieke Universiteit Leuven, K.U Leuven R&D, Panasonic
  • Publication number: 20130072124
    Abstract: A method of analog beamforming in a wireless communication system is disclosed. The system has a plurality of transmit antennas and receive antennas. In one aspect, the method includes determining information representative of communication channels formed between a transmit antenna and a receive antenna of the plurality of antennas, defining a set of coefficients representing jointly the transmit and the receive beamforming coefficients, determining a beamforming cost function using the information and the set of coefficients, determining an optimized set of coefficients by exploiting the beamforming cost function, and separating the optimized set of coefficients into optimized transmit beamforming coefficients and optimized receive beamforming coefficients.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 21, 2013
    Applicants: Katholieke Universiteit Leuven, IMEC
    Inventors: IMEC, Katholieke Universiteit Leuven
  • Publication number: 20130052815
    Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.
    Type: Application
    Filed: October 16, 2012
    Publication date: February 28, 2013
    Applicants: IMEC, Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd.
    Inventors: IMEC, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Company, L
  • Publication number: 20130036829
    Abstract: An optical shear sensor that includes a first and second outer surface at opposing sides and a sensing element is disclosed. In one aspect, the sensing element has an optoelectronic source for emitting light of a predetermined wavelength and having a source front surface where light exits the optoelectronic source, and a photodetector for detecting light of the predetermined wavelength and having a detector front surface where light of the optoelectronic source is received. The optoelectronic source is positioned along the first outer surface and emits light towards the second outer surface. A flexible sensing layer transparent to the predetermined wavelength covers the front surface of the optoelectronic source and the front surface of the photodetector. Upon application of a shear stress, the sensing layer deforms elastically and the outer surfaces are displaced along directions parallel to each other and the source front surface so the intensity of light detected by the photodetector changes.
    Type: Application
    Filed: October 2, 2012
    Publication date: February 14, 2013
    Applicants: Universiteit Gent, IMEC
    Inventors: IMEC, Universiteit Gent
  • Publication number: 20130024737
    Abstract: A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.
    Type: Application
    Filed: September 25, 2012
    Publication date: January 24, 2013
    Applicants: Stichting IMEC Nederland, IMEC
    Inventors: IMEC, Stichting IMEC Nederland