Patents by Inventor In Goo Kang

In Goo Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240371383
    Abstract: A method and apparatus for encoding/decoding audio signal are provided. The encoding method includes transforming an input audio signal in a time domain into an audio signal in a frequency domain, quantizing energy of a frequency band of the audio signal in the frequency domain, generating a normal signal by normalizing the audio signal in the frequency domain according to quantized energy, obtaining a feature vector including information on the energy of the frequency band based on the normal signal and the input audio signal, quantizing the feature vector, obtaining a scale factor used to scale the normal signal based on the quantized feature vector, quantizing an adjustment signal into which the normal signal has been scaled based on the scale factor, and outputting bitstreams based on the quantized energy, the quantized feature vector, and the quantized adjustment signal.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 7, 2024
    Applicants: Electronics and Telecommunications Research Institute, UIF (University Industry Foundation), Yonsei University
    Inventors: Inseon JANG, Seung Kwon BEACK, Jongmo SUNG, Tae Jin LEE, Woo-taek LIM, Byeongho CHO, Hong-Goo KANG, Byeong Hyeon KIM, Jihyun LEE, Hyungseob LIM
  • Publication number: 20240353382
    Abstract: The present application provides a verification method and system of a sample introduction device dedicated to gas chromatography for precisely measuring a concentration of atmospheric greenhouse gas. The verification method of a sample introduction device dedicated to gas chromatography for precisely measuring a concentration of atmospheric greenhouse gas includes the steps of: 1) calculating, by a bias size calculation unit, a degree of bias in a tedlar bag using a correlation between a bias of Pbag to Pcyl and a bias of xbag to xcyl; and 2) determining, by a device performance determination unit, a device having the smallest value of a size of the bias calculated from the bias size calculation unit as an optimal device.
    Type: Application
    Filed: April 22, 2023
    Publication date: October 24, 2024
    Inventor: Nam Goo KANG
  • Publication number: 20240332615
    Abstract: The present invention relates to an electrolyte for batteries and a secondary battery. The present invention has an effect of providing a secondary battery having improved charging efficiency and output due to reduced charging resistance and having excellent long-term lifespan and high-temperature capacity retention rate.
    Type: Application
    Filed: December 24, 2021
    Publication date: October 3, 2024
    Inventors: Ji Young CHOI, Min Goo KIM, Sang Ho LEE, Wan Chul KANG, Jong Cheol YUN, Ji Seong HAN, Min Jung JANG
  • Publication number: 20240315064
    Abstract: The present invention relates to a radiation detection device and a method for manufacturing same. The radiation detection device of the present invention comprises: at least one bottom electrode and at least one top electrode disposed spaced apart from each other; and a semiconductor substrate disposed between the bottom electrode and the top electrode, wherein the upper end of the semiconductor substrate includes at least one active layer region, and the active layer region is filled with a nanocomposite including zero-dimensional nanoparticles, conductive polymers, and one-dimensional or two-dimensional conductive nanomaterials.
    Type: Application
    Filed: June 30, 2022
    Publication date: September 19, 2024
    Inventors: Su Jin KIM, Chang Goo KANG, Jeongmin PARK, Young Soo KIM, Han Soo KIM, Hyojeong CHOI, Byeong Hyeok KIM, Jang Ho HA
  • Patent number: 12066185
    Abstract: According to an embodiment, a monitoring device, comprising: a sensor for sensing inflow gas information including a component and a concentration of an inflow gas introduced into a regenerative thermal oxidizer (RTO); and a processor for determining residual gas information including a component and a concentration of a residual gas in the RTO by using the inflow gas information, and updating an inflow amount per unit time of the inflow gas according to a risk level of the RTO determined based on the residual gas information, is provided.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 20, 2024
    Assignee: TAESUNG ENVIRONMENTAL RESEARCH INSTITUTE CO., LTD.
    Inventors: Gi Yeol Yun, Seok Man Kim, Nam Goo Moon, Seong Hee Kang
  • Publication number: 20240271006
    Abstract: A slurry composition may include an abrasive, a solvent, and polyol. The abrasive may include any one of metal oxide, metal nitride, metal oxynitride, and a combination thereof. The polyol may have about 0.01 mM to about 500 mM of a concentration. Thus, high polishing selectivities may be provided between a B—Si layer, a TiN layer and a SiN layer by controlling a polishing rate of the TIN layer.
    Type: Application
    Filed: August 31, 2023
    Publication date: August 15, 2024
    Inventors: Cheol Min Shin, Hyun Goo Kang, Ungyu Paik, Taeseup Song, Hojin Jeong
  • Publication number: 20240262674
    Abstract: A cold water tank for a direct water purifier is provided.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 8, 2024
    Applicant: COWAY CO., LTD.
    Inventors: Hee Joo KANG, Hee Do JUNG, Chan Jung PARK, Jong Hwan LEE, Hyun Kang LEE, Hyun Goo KIM, Yoo Won OH, Da Woon JUNG, Min Chul YONG, Dong Min OH, Seong Min PARK
  • Publication number: 20240258182
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Application
    Filed: April 12, 2024
    Publication date: August 1, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Publication number: 20240249416
    Abstract: Disclosed are a deep learning model optimization method and apparatus for medical image segmentation. A deep learning model optimization method for medical image segmentation includes: (a) initializing a model parameter; (b) updating the model parameter by performing model-agnostic meta learning (MAML) on a model based on sample batch and applying a gradient descent algorithm to a loss function; (c) setting an optimizer parameter as the updated model parameter, performing one-shot meta-learning on the model, and then updating the optimizer parameter by applying the gradient descent algorithm to the loss function; and (d) updating the model parameter by reflecting the updated optimizer parameter.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 25, 2024
    Inventors: Joon Ki PAIK, Yeong Joon KIM, Dong Goo KANG, Yeong Heon MOK, Sun Kyu KWON
  • Publication number: 20240246106
    Abstract: A system for depositing a material is provided. The system includes a die for extruding the material along a principal deposition direction through an opening of the die. The die includes a cavity fluidly connected to the opening, and a flow guide extending through the cavity towards the opening for shaping a flow of the material extruded via the opening and flowing past a side of the flow guide in the cavity. The side of the flow guide comprises a widening side portion of which a width of the widening side portion increases along the principal deposition direction towards the opening.
    Type: Application
    Filed: February 17, 2023
    Publication date: July 25, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Jong Goo PARK, Ki Hun KIM, Kyoung Rok MUN, Jong Woo SHIN, Sung Mo KANG, Jae Pil LEE
  • Publication number: 20240234485
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo KANG, Hyun-suk LEE, Gi-hee CHO
  • Publication number: 20240224525
    Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventors: Hyo Joon Ryu, Young Hwan Son, Seo-Goo Kang, Jung Hoon Jun, Kohji Kanamori, Jee Hoon Han
  • Publication number: 20240190443
    Abstract: An apparatus for providing a vehicle sound includes a communicator configured to communicates with an electronic device, a detector configured to detect driver's driving pattern information and road driving condition information of a vehicle, and a controller coupled to the communicator and the detector. The controller is configured to obtain music information from the electronic device and calculate a music emotional quotient (EQ) index based on the music information, the driver's driving pattern information, and the road driving condition information. The controller is also configured to select a game sound type based on the music EQ index, and provide an emotional sound matched with the game sound type.
    Type: Application
    Filed: July 12, 2023
    Publication date: June 13, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Ki Chang Kim, Sang Jin Hong, Dong Chul Park, Eun Soo Jo, Jeong Goo Kang
  • Patent number: 12009387
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: June 11, 2024
    Assignee: Samsung Electronics, Co. Ltd.
    Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
  • Publication number: 20240164147
    Abstract: A display device includes: a base substrate; a first pixel electrode, a second pixel electrode, and a third pixel electrode arranged on the base substrate to be spaced apart from each other; a pixel defining film on the first pixel electrode, the second pixel electrode, and the third pixel electrode and including a first opening exposing the first pixel electrode, a second opening exposing the second pixel electrode and spaced apart from the first opening, and a third opening exposing the third pixel electrode and spaced apart from the first opening and the second opening; a first organic layer on the first pixel electrode exposed by the first opening; a second organic layer on the second pixel electrode exposed by the second opening; and a third organic layer on the third pixel electrode exposed by the third opening.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Inventors: Sang Shin LEE, Joon Young PARK, Min Goo KANG, Jung Woo KO, Jong Sung PARK, Hong Kyun AHN, Sang Min YI, Sang Woo JO, Young Eun RYU, Yoon Seo LEE
  • Publication number: 20240155842
    Abstract: A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 9, 2024
    Inventors: Hyo Joon RYU, Seo-Goo KANG, Hee Suk KIM, Jong Seon AHN, Kohji KANAMORI, Jee Hoon HAN
  • Patent number: 11978765
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 7, 2024
    Assignee: Samsung Electronics, Co. Ltd.
    Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
  • Patent number: 11960705
    Abstract: A user terminal device and a controlling method thereof are provided. The user terminal device includes a display configured to be divided into a first area and a second area which is larger than the first area with reference to a folding line, a cover disposed on a rear side of the display, a detector configured to detect a user interaction on the display and the cover, and a controller configured to, in response to the display being folded along the folding line such that the first area and the second area face each other, control the detector to detect a user interaction through an exposure area, which is an exposed part of the second area, and the cover, and, in response to the display being folded such that the two parts of the cover face with each other with reference to the folding line, control the detector to detect a user interaction through the first area and the second area.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-goo Kang, Yun-kyung Kim, Yong-yeon Lee, Ji-yeon Kwak, Hyun-jin Kim
  • Patent number: 11963357
    Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kohji Kanamori, Seo-Goo Kang, Hyo Joon Ryu, Sang Youn Jo, Jee Hoon Han
  • Patent number: 11963358
    Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Joon Ryu, Young Hwan Son, Seo-Goo Kang, Jung Hoon Jun, Kohji Kanamori, Jee Hoon Han