Abstract: A DLNA device for performing a DLNA service scenario, comprises a display unit, an input unit, a communicator and a controller. The display unit is configured to display a user interface for performing the DLNA service scenario. The input unit is configured to receive, from a user, an operational instruction for the user interface. The communicator is configured to communicate with a DLNA network. The controller is configured to control the user interface displayed on the display unit and control the communicator. The user interface is configured to include a main layer providing an interface for media content selection, a first sublayer providing an interface for media server selection, and a second sublayer providing an interface for media player selection. The first sublayer and the second sublayer are displayed temporarily on at least a portion of the main layer according to the operational instruction.

Abstract: The present invention relates to a dye-sensitized solar cell electrode, and more particularly, to a dye-sensitized solar cell electrode capable of enhancing a bond between a dye and an oxide semiconductor to secure reliability and efficiency of a dye-sensitized solar cell.

Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line.

Abstract: A method of determining a quantization parameter includes determining an adjustment range of a quantization parameter correction value based on a size of a motion area of an input image, calculating an average bitrate value of the input image, and adjusting the quantization parameter correction value by decreasing the quantization parameter correction value within the adjustment range in response to determining that the average bitrate value is greater than an upper limit value, and by increasing the quantization parameter correction value within the adjustment range in response to determining that the average bitrate value is equal to or less than a lower limit value.

Abstract: An image sensor configured to provide improved reliability may include a charge passivation layer that includes a multiple different elements, each element of the different elements being a metal element or a metalloid element. The different elements may include a first element of a first group of periodic table elements and a second element of a second, different group of periodic table elements. The charge passivation layer may include an amorphous crystal structure.

Abstract: A DLNA device for sharing multiple home media content comprises a display unit, an input unit, a communicator, a controller and a data storage unit. The display unit is configured to display a user interface for implementing at least one individual DLNA service scenario. The input unit is configured to receive a DLNA service scenario selection information including server selection information, content selection information and player selection information through the user interface. The communicator configured to communicate with a DLNA network. The controller is configured to perform the at least one individual DLNA service scenario based on the DLNA service scenario selection information received through the input unit. The data storage unit configured to store scenario selection information, uniform resource identifier (URI) information of a content and playback state information corresponding to each individual DLNA service scenario.

Abstract: An image sensor includes a semiconductor substrate providing a plurality of pixel regions, a semiconductor photoelectric device disposed in each of the plurality of pixel regions, an organic photoelectric device disposed above the semiconductor photoelectric device, and a pixel circuit disposed below the semiconductor photoelectric device. The pixel circuit includes a plurality of driving transistors configured to generate a pixel voltage signal from an electric charge generated in the semiconductor photoelectric device and the organic photoelectric device. A driving gate electrode of at least one of the plurality of driving transistors has a region embedded in the semiconductor substrate.

Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.

Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

Abstract: The present invention relates to a method for manufacturing a low density inorganic powder insulator having a low density molded structure using expanded perlite without a binder and a mold machine for manufacturing the same, and more particularly, to a technology of uniformly dispersing perlite particles having a shape of irregular fragments of glass using expanded perlite to form a framework among synthetic silica to improve molding strength even at a low density, thereby reducing thermal conductivity (conduction and convection blocking) due to a low density and an increase in a specific surface area.

Abstract: This invention relates to a lead-free solder alloy composition and a method of preparing a lead-free solder alloy, wherein the lead-free solder alloy composition includes a ceramic powder added to a lead-free solder of Sn-(0.1 to 2) wt % Cu, Sn-(0.5 to 5) wt % Ag, or Sn-(0.1 to 2) wt % Cu-(0.5 to 5) wt % Ag. According to this invention, a novel lead-free solder alloy, which functions as a replacement for a conventional lead-free solder, is provided, thus exhibiting superior spreadability, wettability, and mechanical properties than a conventional lead-free solder.

Abstract: A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

Abstract: In a reactor for solid ammonium salt, a method of controlling the reactor, and a NOx emission purification system using solid ammonium salt and selective catalytic reduction, the reactor includes a first chamber and a second chamber. The first chamber has an exhaust and a first heating element. Solid ammonium salt is in the first chamber. The second chamber has a second heating element and is formed at a side of the first chamber. The first chamber is connected with the second chamber. Solid ammonium salt is in the second chamber. An amount of the solid ammonium salt in the second chamber is more than that in the first chamber, so that the first chamber is heated and cooled faster than the second chamber.

Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.

Abstract: A method of controlling a resistive memory device includes: accessing a first pulse power specification satisfying a memory cell coefficient associated with at least a first of a plurality of memory cells included in a memory cell array; generating a first pulse power according to the accessed first pulse power specification; and performing a write operation on at least the first of the plurality of memory cells using the generated first pulse power.

Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.

Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line. Thus, although a crack may be generated in the corner of the semiconductor substrate by twice cutting processes of a wafer, the crack detection circuit may not detect the crack.

Abstract: A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection.

Abstract: A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to a memory cell based on the temperature, setting a level of a reset voltage for reset writing to the memory cell based on the temperature, and performing a write operation on the memory cell based on the level of the set voltage or current and the level of the reset voltage. The memory device may be a resistive memory device.

Abstract: The present invention relates to a technology of reducing nitrogen oxide (NOx) which is harmful discharge gas discharged from an internal combustion engine or a combustor, and to an exhaust gas purification system which inputs solid ammonium salt such as ammonium carbamate or ammonium carbonate into a reactor, thermally decomposes and converts the solid ammonium salt into the ammonia by using engine cooling water, exhaust gas, or an electric heater, which are installed in the reactor, and reduces the nitrogen oxide included in the exhaust pipe on a selective catalytic reduction into nitrogen by injecting the ammonia by using a pressure regulator and a dosing valve.