Abstract: Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data.

Abstract: A method of creating a global coordinate of a polyhedral hollow frame includes a first step of providing a plurality of transmitters on a reference surface in the hollow frame, providing a plurality of reference sensors to create the coordinate of the reference surface, and creating a local coordinate frame of the reference surface on the basis of the positional coordinates measured by the reference sensors; a second step of providing reference sensors at common points of a first vertical surface neighboring to the reference surface to measure and store the coordinates of the common points; a third step of providing a plurality of transmitters and reference sensors on the first vertical surface neighboring to the reference surface to create a local coordinate frame of the first vertical surface; a fourth step of transforming the local coordinate frames created at the first and the third steps into a global coordinate frame using the coordinates of the common points measured at the second step; a fifth step of

Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

Abstract: A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract: A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

Abstract: Provided are memory devices and memory data read methods. A method device may include: a multi-bit cell array; a decision unit that may detect threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages, using a first decision value; an error detector that may detect an error bit of the first data; and a determination unit that may determine whether the decision unit decides second data from the detected threshold voltages using a second decision value, based on a number of detected error bits, the second decision value being different from the first decision value. Through this, it is possible to reduce time spent for reading data stored in the multi-bit cell.

Abstract: A battery module for a rechargeable battery. The battery module has low contact resistance and includes: a plurality of electrode assemblies incorporating a positive electrode, a negative electrode and a separator disposed between the positive electrode and the negative electrode; a housing installed with the electrode assembly; and at least one conductive barrier inserted in the housing thereby dividing the space inside the housing, and electrically connecting the plurality of electrode assemblies.

Abstract: A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.

Abstract: Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

Abstract: Provided is an apparatus and method for collaborative location awareness based on weighted maximum likelihood estimation (MLE), which is configured to improve accuracy of location awareness between nodes in estimating a location of a blind node. The method includes exchanging location awareness information with a reference node and a location-estimated blind node among peripheral nodes when location awareness is requested, performing location estimation based on weighted MLE, performing location calculation by using the location awareness information and an estimate obtained through the location estimation, and providing location awareness results of blind nodes.

Abstract: An electrolyte for a lithium secondary battery is provided. The electrolyte improves battery safety, high temperature storage characteristics, and electrochemical properties of lithium batteries. The electrolyte comprises at least one lithium salt and a non-aqueous organic solvent comprising a cyclic carbonate and a lactone-based compound. The lactone based compound comprises substituents selected from the group consisting of alkyl groups, alkenyl groups, alkynyl groups, aryl groups, and combinations thereof. A lithium battery is also provided, which comprises a negative electrode capable of intercalating/deintercalating lithium, a positive electrode capable of intercalating/deintercalating lithium, and an inventive electrolyte.

Abstract: A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.

Abstract: A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract: A three-dimensional measurement system using an IGPS includes a rescale bar having linear scales thereon, a linear encoder for measuring an absolute length within which the linear encoder moves on the rescale bar, a plurality of optical transmitters that radiates pan beams, and a vector bar having one end attached to the linear encoder, and having a receiver to detect the pan beams radiated from the optical transmitters, the vector bar acquiring coordinates of two points where the vector bar moves by using the receiver, and measuring a relative length from the coordinates. A ratio between the absolute length and the relative length is applied in rescaling an actual distance between two positions to be measured.

Abstract: Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates.

Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

Abstract: A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.

Abstract: Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.