Patents by Inventor In Kwon Jeong

In Kwon Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090002482
    Abstract: A method and apparatus for displaying a three dimensional (3D) video are provided. The apparatus includes a video processor which splits a 3D video signal into a left video signal and a right video signal, and a driver which displays the split left video signal and right video signal on some lines of a display. Accordingly, the 3D video may be displayed on a general display apparatus.
    Type: Application
    Filed: March 20, 2008
    Publication date: January 1, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Bong-hwan CHO, Jae-kwon Jeong
  • Patent number: 7462881
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 9, 2008
    Assignee: LG Electronics Inc.
    Inventors: Jong-Lam Lee, In-kwon Jeong, Myung Cheol Yoo
  • Publication number: 20080225038
    Abstract: A display apparatus having a plurality of input terminals is provided. The display apparatus includes a plurality of input terminals, and an output unit for displaying on a screen a graphic image corresponding to the arrangement of the plurality of input terminals. Graphic images corresponding to an arrangement of the plurality of input terminals provided in the display apparatus are displayed on a screen so that a user can easily determine a connection state of the external apparatus. A method for displaying a graphic image corresponding to an arrangement of the input terminals of a display apparatus is also provided.
    Type: Application
    Filed: August 29, 2007
    Publication date: September 18, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae-kwon JEONG
  • Publication number: 20080151662
    Abstract: A leakage current control device of a semiconductor memory device is provided to effectively remove leakage current flowing from a bit line to a word line when a process defect is generated by gate residues of the semiconductor memory device, thereby reducing unnecessary current consumption. In the leakage current control device, the bit line boosted to a voltage level of core voltage/2 is controlled at a ground voltage level during a precharge period to remove unnecessary leakage current flowing from the bit line to a word line bridge.
    Type: Application
    Filed: March 7, 2008
    Publication date: June 26, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sung Soo XI, Chae Kyu Jang, Hoe Kwon Jeong
  • Publication number: 20080116410
    Abstract: There is provided a buffered rotary valve in which a valve is additionally installed in a rotary valve for supplying a fluid of high pressure and a fluid of low pressure being input from a compressor, thereby reducing the amount of fluid being supplied and unnecessarily consumed, and enhancing the efficiency of a freezing system.
    Type: Application
    Filed: January 25, 2007
    Publication date: May 22, 2008
    Inventors: Sang Kwon Jeong, Je Heon Jeong, Gyu Wan Hwang
  • Patent number: 7374471
    Abstract: An apparatus and method for polishing objects, such as semiconductor wafers, utilizes one or more pivotable load-and-unload cups to transfer the objects to and/or from one or more object carriers to polish the objects. Each pivotable load-and-unload cup may be configured to transfer the objects to and/or from a single object carrier. Alternatively, each pivotable load-and-unload cup may be configured to transfer the objects to and/or from two object carriers. The pivotable load-and-unload cups may be configured to be pivoted about one or more pivoting points over at least one polishing surface, such as a polishing pad surface.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: May 20, 2008
    Assignee: Inopla Inc.
    Inventor: In Kwon Jeong
  • Patent number: 7367866
    Abstract: An apparatus and method for polishing objects, such as semiconductor wafers, utilizes pivotable load/unload cups to transfer the objects to object carriers to polish the objects on at least one polishing surface. The pivoting axes of the pivotable load/unload cups are located between the object carriers.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: May 6, 2008
    Assignee: InoPla Inc
    Inventor: In Kwon Jeong
  • Patent number: 7364496
    Abstract: A polishing head and method for handling and polishing semiconductor wafers uses a base structure with at least one recess region and an outer flexible membrane that can conform to the at least one recess region to form at least one depression to hold a semiconductor wafer onto the outer flexible membrane when suction is applied to the at least one depression.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: April 29, 2008
    Assignee: Inopla Inc.
    Inventors: David E. Berkstresser, Jerry J. Berkstresser, Jino Park, In-Kwon Jeong
  • Publication number: 20080056038
    Abstract: A semiconductor memory device is able to control a timing of an auto-precharge operation. The semiconductor memory device includes a timing controller and an auto-precharge controller. The timing controller generates timing control signals to be used for controlling a timing of an auto-precharge operation based on control signals inputted from an external device or through a mode register set. The auto-precharge controller controls the auto-precharge operation in response to the timing control signals.
    Type: Application
    Filed: June 26, 2007
    Publication date: March 6, 2008
    Inventor: Hoe-Kwon Jeong
  • Publication number: 20080051014
    Abstract: A polishing apparatus for polishing semiconductor wafers comprises a main polishing structure, which includes a plurality of polishing tables, a plurality of polishing heads and a plurality of load-and-unload stations, and an add-on polishing structure, which includes an additional polishing table and an additional polishing head. The add-on polishing structure can be attached to the main polishing structure to form a larger polishing structure with the additional polishing table and the additional polishing head.
    Type: Application
    Filed: June 12, 2007
    Publication date: February 28, 2008
    Inventors: In-Kwon Jeong, David E. Berkstresser
  • Publication number: 20080038993
    Abstract: An apparatus and method for polishing semiconductor wafers uses multiple polishing surfaces, multiple polishing heads and multiple wafer stations to sequentially polish the semiconductor wafers. The wafer stations includes at least one wafer load-unload station to transfer the semiconductor wafers between the wafer load-unload station and the polishing heads.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 14, 2008
    Inventor: In-Kwon Jeong
  • Publication number: 20080014842
    Abstract: A polishing head and method for chucking a semiconductor wafer onto the polishing head uses a base structure and an outer flexible membrane with at least a first annular chamber and a second annular chamber positioned between the base structure and the outer flexible membrane. The polishing head includes a central cavity positioned below the base structure and at least partly defined by the outer flexible membrane, which is used to hold the semiconductor wafer onto the outer flexible membrane.
    Type: Application
    Filed: July 6, 2007
    Publication date: January 17, 2008
    Inventors: David Berkstresser, Jerry Berkstresser, Jino Park, Hanjoo Lee, In-Kwon Jeong
  • Publication number: 20080002804
    Abstract: A semiconductor memory device includes a mode register set circuit having a changeable default value. The mode register set circuit, the default value of which is changeable, includes a signal input unit for latching an input signal, a storage unit driven by an initializing signal for setting the default value to a logic high or low state as required, and an output unit for latching an output of the storage unit.
    Type: Application
    Filed: December 28, 2006
    Publication date: January 3, 2008
    Inventor: Hoe-Kwon Jeong
  • Publication number: 20080001166
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Application
    Filed: September 5, 2007
    Publication date: January 3, 2008
    Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
  • Publication number: 20070295986
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Application
    Filed: August 30, 2007
    Publication date: December 27, 2007
    Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Yoo
  • Patent number: 7306002
    Abstract: A system and method for cleaning a substrate, such as a semiconductor wafer, utilizes a rotatable wafer supporting assembly with a cylindrical body to provide stability for the substrate being cleaned, even at high rotational speeds. The rotatable wafer supporting assembly may include wafer holding mechanisms with pivotable confining members that are configured to hold the substrate using centrifugal force when the wafer supporting assembly is rotated. In an embodiment, the cleaning system may include a positioning system operatively connected to an acoustic transducer to provide meaningful control of the acoustic energy applied to a surface of the substrate by selectively changing the distance between the acoustic transducer and the substrate surface so that the substrate can be cleaned more effectively.
    Type: Grant
    Filed: January 4, 2003
    Date of Patent: December 11, 2007
    Inventors: Yong Bae Kim, Jungyup Kim, Yong Ho Lee, In Kwon Jeong
  • Patent number: 7294531
    Abstract: Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon Hwang, Dong-Kuk Kim, Ki-Kwon Jeong
  • Publication number: 20070207709
    Abstract: A polishing head and method for handling and polishing semiconductor wafers uses a base structure with at least one recess region and an outer flexible membrane that can conform to the at least one recess region to form at least one depression to hold a semiconductor wafer onto the outer flexible membrane when suction is applied to the at least one depression.
    Type: Application
    Filed: February 28, 2007
    Publication date: September 6, 2007
    Inventors: David E. Berkstresser, Jerry J. Berkstresser, Jino Park, In-Kwon Jeong
  • Patent number: 7262114
    Abstract: A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed thereon, and then the wafer is cut to separate the chips from one another. Each semiconductor chip is then placed on and attached to a die pad of a base frame, while the warpage prevention material is detached from the semiconductor chip. Thus, the warpage prevention material is removed without requiring a process that is extraneous to the die attaching process.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: August 28, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-kwon Jeong, Hyeon Hwang
  • Patent number: 7258124
    Abstract: An apparatus and method for treating surfaces of semiconductor wafers with a reactive gas, such as ozone, utilizes streams of gaseous material ejected from a gas nozzle structure to create depressions on or holes through a boundary layer of processing fluid formed on a semiconductor wafer surface to increase the amount of reactive gas that reaches the wafer surface through the boundary layer. The apparatus and method may be used to clean a semiconductor wafer surface and/or grow an oxide layer on the wafer surface by oxidation.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: August 21, 2007
    Inventors: In Kwon Jeong, Yong Bae Kim, Jungyup Kim