Patents by Inventor In Kwon Jeong

In Kwon Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for polishing objects using object cleaners
    Patent number: 7674154
    Abstract: An apparatus and method for polishing objects, such as semiconductor wafers, uses at least one object cleaner, which may be a movable object cleaner. The movable object cleaner allows access to different parts of the apparatus for maintenance.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: March 9, 2010
    Assignee: KoMiCo Technology, Inc.
    Inventor: In Kwon Jeong
  • Natural Gas Liquefaction System with Turbine Expander and Liquefaction Method Thereof
    Publication number: 20100024475
    Abstract: A natural gas liquefaction system with a turbine expander is provided that can improve the efficiency of the whole refrigeration cycle by using the turbine expander, instead of the throttling process that uses the conventional Joule-Thomson throttling valve that is used as a final throttling means in a conventional natural gas liquefaction system, and a liquefaction method thereof. The natural gas liquefaction cycle provided with the turbine expander of the present invention comprises a compressor 100, at least one vapor-liquid separator 300 or 310, a plurality of heat exchangers 200, 210, 220, 230 and 240, at least one Joule-Thomson throttling valves (below to be called JT valve) 400 and 410, a turbine expander 500, and connecting lines composed of plurality of pipes P1, P2, P3, P4, P5, P6 and P7 to connect these components.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sang Kwon Jeong, Gyu Wan Hwang, Seung Whan Baek
  • APPARATUS AND METHOD FOR POLISHING SEMICONDUCTOR WAFERS USING ONE OR MORE POLISHING SURFACES
    Publication number: 20100009599
    Abstract: An apparatus and method for polishing objects, such as semiconductor wafers, utilizes one or more polishing surfaces, multiple wafer carriers and at least one load-and-unload cup. The load-and-unload cup may be configured to move to and from the wafer carriers in a pivoting manner. The load-and-unload cup may be configured to move to and from the wafer carriers in a linear reciprocating manner. The wafer carriers may be configured to move to and from the load-and-unload cup in a pivoting manner. The wafer carriers may be configured to move to and from the load-and-unload cup in a linear reciprocating manner.
    Type: Application
    Filed: September 22, 2009
    Publication date: January 14, 2010
    Applicant: KOMICO TECHNOLOGY, INC.
    Inventor: In Kwon Jeong
  • Apparatus for Processing a Wafer
    Publication number: 20090321432
    Abstract: An apparatus for processing a wafer includes a chamber, a boat, microwave generators and reflective plates. The boat is disposed in the chamber. One or more wafers are stacked in the boat. One or more microwave generators are connected to the chamber. The microwave generators generate microwaves for heating the wafers. The reflective plates reflect the microwaves onto the wafers such that the microwaves are uniformly applied to the wafers. Each of the reflective plates faces at least one of both sides of the wafer. The reflective plates include at least one of a fat side, a concave side and a convex side.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 31, 2009
    Inventors: II-Young Han, Mitsuo Umemoto, Ki-Kwon Jeong, Won-Keun Kim
  • METHOD FOR ALIGNING WAFER AND ALIGNMENT APPARATUS USING THE METHOD
    Publication number: 20090310137
    Abstract: A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.
    Type: Application
    Filed: February 12, 2009
    Publication date: December 17, 2009
    Inventors: Young-shin Choi, Ki-kwon Jeong
  • Method of fabricating vertical structure LEDs
    Publication number: 20090278161
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Application
    Filed: July 21, 2009
    Publication date: November 12, 2009
    Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Cheol Yoo
  • Apparatus and method for polishing semiconductor wafers using one or more polishing surfaces
    Patent number: 7591711
    Abstract: An apparatus and method for polishing objects, such as semiconductor wafers, utilizes one or more polishing surfaces, multiple wafer carriers and at least one load-and-unload cup. The load-and-unload cup may be configured to move to and from the wafer carriers in a pivoting manner. The load-and-unload cup may be configured to move to and from the wafer carriers in a linear reciprocating manner. The wafer carriers may be configured to move to and from the load-and-unload cup in a pivoting manner. The wafer carriers may be configured to move to and from the load-and-unload cup in a linear reciprocating manner.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: September 22, 2009
    Assignee: KoMiCo Technology, Inc.
    Inventor: In Kwon Jeong
  • Method of fabricating vertical structure LEDs
    Patent number: 7588952
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: September 15, 2009
    Assignee: LG Electronics Inc.
    Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Cheol Yoo
  • Method of fabricating vertical structure LEDs
    Patent number: 7576368
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: August 18, 2009
    Assignee: LG Electronics Inc.
    Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Cheol Yoo
  • Method of fabricating vertical structure LEDs
    Patent number: 7569865
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 4, 2009
    Assignee: LG Electronics Inc.
    Inventors: Jong-Lam Lee, In-kwon Jeong, Myung Cheol Yoo
  • Mode register set circuit
    Patent number: 7570729
    Abstract: A semiconductor memory device includes a mode register set circuit having a changeable default value. The mode register set circuit, the default value of which is changeable, includes a signal input unit for latching an input signal, a storage unit driven by an initializing signal for setting the default value to a logic high or low state as required, and an output unit for latching an output of the storage unit.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: August 4, 2009
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Hoe-Kwon Jeong
  • Method of fabricating vertical structure LEDs
    Patent number: 7563629
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: July 21, 2009
    Assignee: LG Electronics Inc.
    Inventors: Jong-Lam Lee, In-Kwon Jeong, Myung Cheol Yoo
  • METHOD AND APPARATUS FOR TRANSFERRING POSE OF 3-DIMENSIONAL CHARACTERS
    Publication number: 20090153551
    Abstract: A method for transferring a pose from an original digital character to a newly-created digital character, includes: deriving constraints from a pose of the original character; modeling pose characteristics of each joint of the newly-created character as a probability distribution function having an input variable of a rotation angle of corresponding joint; and modeling pose characteristics of all joints of the newly-created character as a joint probability distribution function having input variables of rotation angles of corresponding joints. The method further includes extracting, based on the joint probability distribution function, the rotation angles of all joints of the newly-created character to thereby create a pose of the newly-created character, the rotation angles satisfying the constraints.
    Type: Application
    Filed: October 17, 2008
    Publication date: June 18, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ki-young PARK, Il-Kwon JEONG, Byoung Tae CHOI
  • LOCOMOTION GENERATION METHOD AND APPARATUS FOR DIGITAL CREATURE
    Publication number: 20090153568
    Abstract: A locomotion generation method for a digital creature includes: imaging and capturing movements of a creature placed on a base plate having a printed pattern; extracting body position information, body posture information, leg posture information, and footprint information of the creature by analyzing captured images; and generating creature movement by applying inverse kinematics to the body position information, the body posture information, the leg posture information, and the footprint information of the creature.
    Type: Application
    Filed: February 20, 2008
    Publication date: June 18, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Il-Kwon Jeong, Man Kyu Sung, Byoung Tae Choi
  • ALIGNMENT INSPECTION METHOD AND ALIGNMENT INSPECTION APPARATUS
    Publication number: 20090141275
    Abstract: A method of inspecting the alignment of a second structure with respect to a first structure, including emitting light from a first plane of a first structure to a second plane of a second structure in a first direction perpendicular to the first plane of the first structure, the first plane and the second plane facing each other. The incident light can be reflected from the second plane toward the first plane in a second direction parallel with the first direction. The position of the reflected light can be detected to inspect the alignment of the second structure with respect to the first structure.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 4, 2009
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Il-Young HAN, Mitsuo Umemoto, Ki-Kwon Jeong, Young-shin Choi
  • REFLOW APPARATUS AND METHOD
    Publication number: 20090134202
    Abstract: Provided are a reflow apparatus and method. The reflow apparatus includes a loader unit, a heating unit, an unloader unit, and a moving unit. The loader unit has an input module and an input stacker. Processing objects are stored in vertical stacks in magazines, and a plurality of magazines is stored in the input stacker. The magazines stored in the input stacker are moved to the input module and are introduced into the heating unit by the moving unit. Solder balls provided on the processing objects within the heating unit are quickly processed using an induction heating method. The processing objects that have undergone a reflow process are loaded in a magazine on an output module of the unloader unit and are then stored in an output stacker.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 28, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Ill KIM, Il-Young HAN, Ki-Kwon JEONG
  • IN-LINE PACKAGE APPARATUSES AND METHODS
    Publication number: 20090127314
    Abstract: An in-line package apparatus includes a first treating unit, an input storage unit, a heating unit and an output storage unit. The first treating unit performs a ball attach process or a chip mount process. A processing object that a process is completed in the first treating unit is received in a magazine so as to be vertically stacked and a plurality of magazines each having one or more processing objects is stored in an input stacker. The heating unit performs a reflow process on the processing objects in the magazine stored in the input stacker by an induction heating method. A processing object that a reflow process is completed is received in a magazine and then stored in an output stacker.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 21, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-Ill KIM, Jong-Gi Lee, Kwang-Yong Lee, Ki-Kwon Jeong
  • POLISHING APPARATUS AND METHOD FOR POLISHING SEMICONDUCTOR WAFERS USING LOAD-UNLOAD STATIONS
    Publication number: 20090061739
    Abstract: A polishing apparatus and method for polishing semiconductor wafers uses multiple load-unload stations and at least one turn-over robotic wafer handing device to process the wafers so that the wafer can be polished at multiple polishing tables. The turn-over robotic wafer handing device operates to turn over the wafers so that one side of the wafers can be polished at a first polishing table and the other side of the wafers can then be polished at a second polishing table.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 5, 2009
    Inventor: In-Kwon Jeong
  • Method of forming a thin wafer stack for a wafer level package
    Patent number: 7494845
    Abstract: A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: February 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon Hwang, Ki-Kwon Jeong
  • Method for manufacturing semiconductor wafer
    Patent number: 7479455
    Abstract: A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: January 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Kwon Jeong, Hyeon Hwang