Abstract: An internal voltage generation circuit may include an oscillation circuit, a signal generation circuit, and a pumping circuit. The oscillation circuit may generate an oscillation signal. The signal generation circuit may generate first and second pumping driving signals on the basis of the oscillation signal. The pumping circuit may generate a pumping voltage through a pumping operation on the basis of the first and second pumping driving signals.

Abstract: An air-cooled battery cooling system for an air mobility vehicle may ensure the cooling performance for batteries using air flows during the flight of the air mobility vehicle, since the cooling of the batteries is performed using an air flow in the top-bottom direction due to the hovering of the air mobility vehicle and an air flow in the front and rear direction due to the cruising of the air mobility vehicle, the efficient cooling performance for the batteries is ensured in a variety of flight modes. Furthermore, the batteries are securely fixed while being cooled by air flows via the heat transfer pads within the battery packs.

Abstract: A hybrid air mobility vehicle can make a long-distance flight through an efficient operation of an engine and a battery, and can reduce discomfort by reducing noise according to flight surroundings. The hybrid air mobility vehicle includes: an engine and a generator; a battery and a drive motor electrically connected to the generator; a first propeller connected to the drive motor and a second propeller connected to the generator through a clutch; and a controller that controls driving of the engine, the clutch, and the drive motor, based on a flight factor including at least one of a flight mode, a required power, a battery charging amount, or a surrounding flight environment of the hybrid air mobility vehicle.

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

Abstract: According to an embodiment, a semiconductor device comprises a first monitoring pad and a second monitoring pad; a test circuit including an NMOS transistor having a drain and source coupled between a first voltage terminal and a common node, a PMOS transistor having a drain and source coupled between the common node and a second voltage terminal, a first switching element having a first terminal coupled to the common node via a first resistor and a second terminal coupled to the first monitoring pad, and a second switching element having a third terminal coupled to the common node via a second resistor and a fourth terminal coupled to the second monitoring pad; and a test control circuit suitable for controlling the test circuit.

Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.

Abstract: A method for wirelessly connecting devices performed in a wireless connection system implemented with a computer includes: providing a list of devices capable of remote access with a user account of a user; connecting devices based on the list of devices capable of remote access; automatically updating a list of folders in the connected devices and a list of files included in the folders; and integrally managing files included in the connected devices.

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

Abstract: An apparatus for generating thrust for air transport includes a main thrust device, and an auxiliary thrust device configured to generate auxiliary thrust so as to enable an aircraft to vertically take off and land. The apparatus further includes: wings fixed to left and right sides of a fuselage of the aircraft, rotors installed on the wings and configured to generate thrust. In particular, the main thrust device provides driving force to the rotors using motors and an engine, and the auxiliary thrust device is installed in the fuselage and has a center of gravity configured to coincide with a center of gravity of the aircraft.

Abstract: In an air mobility vehicle, an engine operates as required to provide mechanical driving force or electric energy. A battery is charged with the electric energy from the engine. Main rotors operate using the electric energy of the battery and electric power generated by the engine to perform takeoff, landing, and cruising. Auxiliary rotors are disposed at or adjacent to the center of gravity of a vehicle body and mechanically connected to the engine via a clutch. The auxiliary rotors perform the takeoff, the landing, or the cruising by receiving the mechanical driving force from the engine when the clutch is in an engaged position. A controller monitors the states of the battery and the main rotors and controls the operations of the engine and the clutch.

Abstract: A method for determining a motor angle, may include deriving a sensor weight and a sensorless weight via a cross product of an actual current vector and a model-based sensored current vector and a cross product of the actual current vector and a model-based sensorless current vector; and determining a final motor angle by applying the sensor weight and the sensorless weight to each of a sensored angle and a sensorless angle.

Abstract: A semiconductor package includes a first semiconductor chip having a first face and a second face opposite thereto. The first semiconductor chip includes a first wiring layer having a surface that forms the first face. A second semiconductor chip disposed on the first face of the first semiconductor chip includes a second wiring layer directly contacting the first wiring layer. A first mold layer is disposed on one lateral side of the first semiconductor chip and directly contacts the second wiring layer. A first via penetrates the first mold layer. A width of the first wiring layer and the first semiconductor chip in a horizontal direction are substantially the same. A width of the second wiring layer and the second semiconductor chip in the horizontal direction are substantially the same. A height of the first via and the first semiconductor chip in the vertical direction are substantially the same.

Abstract: A storage device assembly is provided. The storage device assembly includes a latch assembly having a body and a hook mounted on the body, the hook having elasticity and having distal ends thereof bend away from the body; and a storage device to be joined to the latch assembly. The storage device includes a memory module including a memory connector, and a first enclosure and a second enclosure that encase the memory module except for an opening through which the memory connector is accessible. The first enclosure includes fixing holes corresponding to the distal ends of the hook and configured to accommodate the distal ends of the hook in a configuration in which the storage device is joined to the latch assembly.

Abstract: A method of recognizing an object, and a device therefor are provided. The method includes obtaining first sensing data from a first sensor that senses the object, obtaining second sensing data from a second sensor that senses the object, obtaining a first object recognition reliability for the object and a second object recognition reliability for the object respectively based on the first sensing data and the second sensing data, based on the first object recognition reliability and the second object recognition reliability, matching object information of the object recognized using the second sensing data to the first sensing data, and storing the matched object information in a database of one of the first sensor and the second sensor.

Abstract: A motor apparatus has a cooling structure capable of effectively cooling the motor by inducing a fluid flow into the motor. In particular, the motor apparatus includes: a first part having a first flow path and a motor installed thereon; a second part having a second flow path and configured to be rotatably mounted on the first part and connected to the motor; and a turbine portion coupled to the second part and including disks stacked on one another forming spaces therebetween. When the turbine portion is rotated together with the second part, air is drawn through the first flow path or the second flow path and introduced into an opening hole of each of the disks, and the air is discharged into the spaces formed between the respective disks to cool the motor.

Abstract: A method for measuring blood sugar that is performed by an apparatus for measuring blood is provided. The method includes calculating color data from multiple skin regions of interest in a skin image, classifying a user's meal state into a pre-meal state or a post-meal state through analysis of acquired user information, estimating blood sugar by applying the calculated color data to a blood sugar regression linear equation corresponding to the classified user's meal state, and measuring robust blood sugar by weighted averaging the estimated blood sugar.

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.

Abstract: According to an embodiment, a semiconductor device comprises a first monitoring pad and a second monitoring pad; a test circuit including an NMOS transistor having a drain and source coupled between a first voltage terminal and a common node, a PMOS transistor having a drain and source coupled between the common node and a second voltage terminal, a first switching element having a first terminal coupled to the common node via a first resistor and a second terminal coupled to the first monitoring pad, and a second switching element having a third terminal coupled to the common node via a second resistor and a fourth terminal coupled to the second monitoring pad; and a test control circuit suitable for controlling the test circuit.

Abstract: A method of operating a storage device that is connected to a host includes entering an authentication mode; and performing the authentication operation responsive to entering the authentication mode. The performing of the authentication operation includes receiving a read command and a first random authentication address from the host; performing an authentication procedure based on at least a portion of the first random authentication address; and generating result data responsive to performing the authentication algorithm.

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.