Abstract: In a peer aware communication network, a method in which a peer device accesses a link includes: determining a phase based on service which is provided to another peer device; and accessing a link which is included in a superframe that a predetermined length according to the phase, a method of reserving resources and a method of avoiding interference are provided.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.

Abstract: A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.

Abstract: Disclosed herein are a method and apparatus for representing a bubble effect using metadata. The method for representing a bubble effect using a bubble effect representation apparatus may include generating metadata based on information related to a bubble effect, information about the performance of the bubble effect representation apparatus, and preference information for the bubble effect, generating control instruction information for the bubble effect representation apparatus by analyzing the generated metadata, and representing the bubble effect based on the control instruction information.

Abstract: An emotion information conversion apparatus and method is provided. The emotion information conversion apparatus includes a visual information extractor to extract visual information from an input image, an emotion information converter to analyze the extracted visual information and convert the visual information into emotion information, and a sensory effect information generator to generate sensory effect information transferable to a user, based on the converted emotion information.

Abstract: A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.

Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.

Abstract: A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.

Abstract: A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction.

Abstract: A nonvolatile memory device includes a gate structure in which a plurality of interlayer dielectric layers and a plurality of gate electrodes are alternately stacked; a pass gate electrode lying under the gate structure; a sub channel hole defined in the pass gate electrode; a pair of main channel holes defined through the gate structure and communicating with the sub channel hole; a channel layer formed on inner walls of the pair of main channel holes and the sub channel hole; and a metallic substance layer contacting the channel layer in the sub channel hole.

Abstract: A nonvolatile memory device includes a gate structure in which a plurality of interlayer dielectric layers and a plurality of gate electrodes are alternately stacked; a pass gate electrode lying under the gate structure; a sub channel hole defined in the pass gate electrode; a pair of main channel holes defined through the gate structure and communicating with the sub channel hole; a channel layer formed on inner walls of the pair of main channel holes and the sub channel hole; and a metallic substance layer contacting the channel layer in the sub channel hole.

Abstract: A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate contact sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate.

Abstract: A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.

Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Abstract: A method for manufacturing a catheter includes preparing raw materials and maturing the raw materials in a drier at 50-55° C. for 20 days, preparing the expandable member, and the first and second tubes, in forms, by cutting the raw materials, fitting an index ring on the second tube, welding the expandable member to the first tube, and welding the expandable member with the second tube, connecting the first tube to a first side of the manifold, and connecting the second tube to a second side of the manifold, forming a shape and a size of the expandable member, and drying an interior of the expandable member and the second tube and maturing the expandable member for 24 hours in the drier at 50-55° C., then for 48 hours in the drier at 50-55° C.

Abstract: The present invention relates to a method for detecting neuronal injury in a mammalian subject. The biomarker of this invention specifically increases in serum of the mammalian that has neuronal injuries. In addition, the biomarker of this invention permits to identify and predict neuronal injuries.

Abstract: A method for manufacturing a catheter having an expandable member is provided, which includes preparing raw materials with highly elastic thermoplastic polyurethane (TPU), maturing the raw materials in a drier at 50˜55° C.

Abstract: A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction.

Abstract: A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.