Abstract: A display device includes: a pixel connected to each of a first scan line, a second scan line, and a data line; a scan driver supplying a first scan signal to the first scan line and a second scan signal to the second scan line; a controller dividing one frame period into an active period and a blank period and generating a count signal in which a time duration of the blank period is counted and a power control signal; a data driver supplying a data signal to the data line; and a power supply controlling a source driving voltage supplied to the data driver according to a duration of the blank period based on the power control signal. When the count signal reaches a reference value, the controller supplies a start signal for output of the first scan signal to the scan driver.

Abstract: Disclosed are an optical signal communication method and device and a biometric data monitoring system using the optical signal communication method and device. An optical signal communication method performed by an optical signal transmitting device includes receiving current input data to be modulated into an optical signal, dividing the received current input data into a plurality of sub-data sets including first sub-data and second sub-data, modulating the current input data into an optical signal including a start pulse, an intermediate pulse, and an end pulse based on the sub-data sets, and transmitting the optical signal to an optical signal receiving device.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: A display device of the present invention includes a pixel unit including a plurality of pixels connected to data lines and scan lines; a data driver disposed on one side of the pixel unit to drive the data lines; a scan driver disposed on the one side of the pixel unit together with the data driver to drive the scan lines; and a controller which controls an output timing of a data signal in units of pixel columns and units of pixel rows based on a load of a scan signal supplied to the scan lines and a load of the data signal supplied to the data lines.

Abstract: The present invention relates to a new class of cationic linear polyphosphazenes bearing as side groups a hydrophilic poly(ethylene glycol) and a spacer group selected from the group consisting of lysine, oligopeptides containing lysine, amino-ethanol, amino-propanol, amino-butanol, amino-pentanol and amino-hexanol, and the polyphosphazene-drug conjugates comprising hydrophobic anticancer drugs by covalent bonding and the preparation methods thereof. The present polyphosphazene-drug conjugates exhibit outstanding tumor selectivity and low toxicity.

Abstract: A display device includes: a screen saver operable to cause an image to be displayed with a lowered luminance in a screen save mode by lowering a scale factor from a first value based on the image being displayed as a still image longer than a reference time; and an overcurrent protection circuit operable to detect an overcurrent and cause a power of the display device to be turned off based on a predetermined current value that is reduced according to the scale factor and comparison between the predetermined current value and a driving current supplied provided to a display panel in which the image is displayed.

Abstract: A display device according to an embodiment includes a display panel including a plurality of pixels, and an image sticking compensator configured to generate a second image data by reflecting an age data accumulated in a first image data input from an external source. The image sticking compensator generates the age data by accumulating a deterioration data generated by reflecting a frequency weight corresponding to a determined frequency of a previous frame to an image data of the previous frame after the image data of the previous frame is stored.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: The present invention relates to a new class of cationic linear polyphosphazenes bearing as side groups a hydrophilic poly(ethylene glycol) and a spacer group selected from the group consisting of lysine, oligopeptides containing lysine, amino-ethanol, amino-propanol, amino-butanol, amino-pentanol and amino-hexanol, and the polyphosphazene-drug conjugates comprising hydrophobic anticancer drugs by covalent bonding and the preparation methods thereof. The present polyphosphazene-drug conjugates exhibit outstanding tumor selectivity and low toxicity.

Abstract: A display device includes a display panel, a first memory, and a degradation compensator. The first memory device stores stress data including degradation values representing a degradation degree of each of the blocks in the display panel. The degradation compensator loads the stress data from the first memory device, updates the stress data based on current input data and a maximum degradation value, updates the maximum degradation value based on degradation values included in the updated stress data, and generate compensated data by compensating for the current input data based on the updated stress data. The degradation compensator determines whether a first degradation value included in the stress data is normal by comparing the first degradation value with the maximum degradation value, and updates the first degradation value based on at least one adjacent degradation value adjacent to the first degradation value, when the first degradation value is abnormal.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A display device includes: a screen saver operable to cause an image to be displayed with a lowered luminance in a screen save mode by lowering a scale factor from a first value based on the image being displayed as a still image longer than a reference time; and an overcurrent protection circuit operable to detect an overcurrent and cause a power of the display device to be turned off based on a predetermined current value that is reduced according to the scale factor and comparison between the predetermined current value and a driving current supplied provided to a display panel in which the image is displayed.

Abstract: A display device includes a display panel, a first memory, and a degradation compensator. The first memory device stores stress data including degradation values representing a degradation degree of each of the blocks in the display panel. The degradation compensator loads the stress data from the first memory device, updates the stress data based on current input data and a maximum degradation value, updates the maximum degradation value based on degradation values included in the updated stress data, and generate compensated data by compensating for the current input data based on the updated stress data. The degradation compensator determines whether a first degradation value included in the stress data is normal by comparing the first degradation value with the maximum degradation value, and updates the first degradation value based on at least one adjacent degradation value adjacent to the first degradation value, when the first degradation value is abnormal.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A display device includes a display panel, a first memory, and a degradation compensator. The first memory device stores stress data including degradation values representing a degradation degree of each of the blocks in the display panel. The degradation compensator loads the stress data from the first memory device, updates the stress data based on current input data and a maximum degradation value, updates the maximum degradation value based on degradation values included in the updated stress data, and generate compensated data by compensating for the current input data based on the updated stress data. The degradation compensator determines whether a first degradation value included in the stress data is normal by comparing the first degradation value with the maximum degradation value, and updates the first degradation value based on at least one adjacent degradation value adjacent to the first degradation value, when the first degradation value is abnormal.

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Abstract: The display device includes a first pixel connected to a first scan line and a first data line, a second pixel connected to a second scan line and the first data line, a scan driver configured to supply a scan signal to the first scan line and the second scan line, and a data driver connected to the first data line. The data driver provides a first data signal to the first pixel when the scan signal is applied to the first scan line, the data driver provides a second data signal to the second pixel when the scan signal is applied to the second scan line, and a length of a first period in which the first data signal is provided is different from a length of a second period in which the second data signal is provided.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.