Abstract: A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

Abstract: A timing controller includes a data grouping part that generates a plurality of grayscale groups based on input image data, each grayscale group including n×m grayscales, a grayscale classifying part that generates a plurality of grayscale patterns respectively corresponding to the grayscale groups, a grayscale in the grayscale groups being classified in the grayscale patterns as a first grayscale if the grayscale is higher than a first reference grayscale or as a second grayscale if the grayscale is lower than a second reference grayscale, a pattern comparing part that compares each grayscale pattern with a first pattern including the n×m first and second grayscales, a pattern counter that counts a number of patterns of the grayscale patterns that are substantially the same as the first pattern, and a driving mode changing part that changes a driving mode of a display panel when the number is greater than a reference number.

Abstract: A layered channel access method of a Group Representative-station (GR-STA) in a Wireless Local Area Network (WLAN) system is provided. The method includes receiving a management, including setting information indicative of a first phase and a second phase frame, from an Access Point (AP), receiving a first radio frame from the AP or accessing a channel and sending a second radio frame to the AP during the first phase indicated by the setting information, and receiving a third radio frame from an affiliated STA of a group to which the GR-STA belongs or accessing a channel and sending a fourth radio frame to at least one STA of the group to which the GR-STA belongs during the second phase indicated by the setting information.

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract: A gate driver includes a first shift-register including a plurality of odd-numbered stages which outputs a plurality of odd-numbered original gate signals having a pre-charge pulse and a main-charge pulse in synchronization with a first gate clock signal, a second shift-register comprising a plurality of even-numbered stages which outputs a plurality of even-numbered original gate signals having a pre-charge pulse and a main-charge pulse in synchronization with a second gate clock signal, a first inverter configured to output a first inversion pre-charge control signal having a phase opposite to a phase of a first pre-charge control signal, and a second inverter configured to output a second inversion pre-charge control signal having a phase opposite to a phase of a second pre-charge control signal.

Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Abstract: The present invention relates to a new class of cationic linear polyphosphazenes bearing as side groups a hydrophilic poly(ethylene glycol) and a spacer group selected from the group consisting of lysine, oligopeptides containing lysine, amino-ethanol, amino-propanol, amino-butanol, amino-pentanol and amino-hexanol, and the polyphosphazene-drug conjugates comprising hydrophobic anticancer drugs by covalent bonding and the preparation methods thereof. The present polyphosphazene-drug conjugates exhibit outstanding tumor selectivity and low toxicity.

Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract: Disclosed are a method and device for transmitting a frame. The method for transmitting a frame includes a step of generating A-MPDU (aggregate MAC protocol data unit) and a step of transmitting A-MPDU. The A-MPDU includes a first AMPDU subframe and a second A-MPDU subframe, wherein the first A-MPDU subframe includes a data block, and the second AMPDU subframe includes an FEC (Forward Error Correction) coding block which is additionally used in the decoding of the data block. Thus, the STA is capable of preventing unnecessary power consumption of STA by selectively determining whether FEC information is received according to whether an error occurred in the decoded data.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: A method and a device for reporting a modulation and coding scheme (MCS) feedback in a wireless local area network are provided. A responding station receives, from a requesting station, a requesting Physical layer Protocol Data Unit (PPDU) for requesting a MCS feedback via a plurality of spatial streams. A recommended MCS is estimated under an assumption that the requesting station will transmit at least one first spatial stream among the plurality of spatial streams used for the requesting PPDU, The responding station transmits, to the requesting station, the MCS feedback including a recommended MCS field indicating the recommended MCS and a recommended stream field indicating a number of at least one recommended spatial stream. A number of the at least one first spatial stream used for estimating the recommended MCS is equal to the number of the at least one recommended spatial stream.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Abstract: A method of link adaptation performed by an access point supporting multi user (MU) multiple input multiple output (MIMO) in wireless local area network system is provided. The method includes transmitting, to a first station, a physical layer convergence procedure (PLCP) protocol data unit (PPDU) containing a modulation and coding scheme (MCS) request (MRQ) and receiving, from the first station, a MCS feedback (MFB) in response to the MRQ, wherein the first station is one of destination stations of MU-MIMO transmission performed by the access point, and the MFB includes a recommended MCS value computed, by the first station, on the assumption that the first station, as a member of the destination stations, receives data transmitted over at least one spatial stream allocated to the first station in MU-MIMO transmission.

Abstract: A method of communication based on a receive chain control, performed by a receiver, in a wireless local area network is provided. The method includes: receiving a frame from a transmitter, the frame indicating a multi receive chain operation, activating at least one receive chain, each receive chain processing a received signal transmitted through each spatial stream, and receiving at least one data field from the transmitter through the at least one activated receive chain.

Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

Abstract: The present invention relates to a method for transmitting a frame, which is performed by a transmission station in a wireless LAN system that supports frame transmission and reception on the basis of a first physical layer and a second physical layer. The method comprises the steps of: transmitting a request-to-send (RTS) to a reception station through the first physical layer of the transmission station; receiving, by the reception station, a first clear-to-send (CTS) frame transmitted through the first physical layer of the reception station in response to the RTS frame; and transmitting a second CTS frame through the second physical layer of the transmission station, then transmitting a data frame through the first physical layer of the transmission station.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.