Patents by Inventor Inderjit Singh

Inderjit Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6890793
    Abstract: A method for producing a die package is disclosed. A bumped die comprises solder bumps mounted to a leadframe including a first lead comprising a first locating hole and a second lead comprising a second locating hole. The solder bumps are present in the first and second locating holes, and a molding material is formed around the die.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: May 10, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Inderjit Singh
  • Publication number: 20050023700
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventors: Inderjit Singh, Howard Marks, Joseph Greco
  • Publication number: 20040072138
    Abstract: This current invention includes compositions and methods of nitric oxide synthase inhibitors to treat or reduce ischemia/reperfusion injury in a patient. More specifically, the invention relates to a combinational therapy of 5-Aminoimidazole-4-carboxamide-1-B-D-ribonucleoside (AICAR) and N-acetyl cysteine (NAC) to attenuate ischemia/reperfusion injury to a transplanted organ.
    Type: Application
    Filed: May 2, 2003
    Publication date: April 15, 2004
    Applicant: Medical University of South Carolina
    Inventor: Inderjit Singh
  • Publication number: 20030195256
    Abstract: The current invention discloses novel methods for the inhibition of inducible nitric oxide synthesis (iNOS) and the production of NO. Methods of inhibiting the induction of proinflammatory cytokines are also described. Methods of treating various disease states, such as X-linked adrenoleukodystrophy, multiple sclerosis, Alzheimer's and septic shock using inhibitors of iNOS and cytokine induction are disclosed. The inhibitors include the exemplary compounds lovastatin, a sodium salt of phenylacetic acid (NaPA), FPT inhibitor II, N-acetyl cysteine (NAC), and cAMP.
    Type: Application
    Filed: October 18, 2002
    Publication date: October 16, 2003
    Applicant: MUSC Foundation for Research Development
    Inventor: Inderjit Singh
  • Publication number: 20030178717
    Abstract: A flip-chip with a solder pre-plated leadframe that includes locating holes. The leadframe does not include a die attach pad. Two of the leads include a locating or alignment hole for receiving a solder bump of the bumped die. The remaining leads include die contact areas for placement of the die thereon with the solder bumps contacting the die contact areas. The leads with the die contact areas are downset. The downset is approximately 4 mm.
    Type: Application
    Filed: April 17, 2003
    Publication date: September 25, 2003
    Applicant: Fairchild Semiconductor Corporation
    Inventor: Inderjit Singh
  • Patent number: 6580165
    Abstract: A flip-chip with a solder pre-plated leadframe that includes locating holes. The leadframe does not include a die attach pad. Two of the leads include a locating or alignment hole for receiving a solder bump of the bumped die. The remaining leads include die contact areas for placement of the die thereon with the solder bumps contacting the die contact areas. The leads with the die contact areas are downset. The downset is approximately 4 mm.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: June 17, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Inderjit Singh
  • Patent number: 6560597
    Abstract: A system and method operates with a document collection in which documents are represented as normalized document vectors. The document vector space is partitioned into a set of disjoint clusters and a concept vector is computed for each partition, the concept vector comprising the mean vector of all the documents in each partition. Documents are then reassigned to the cluster having their closest concept vector, and a new set of concept vectors for the new partitioning is computed. From an initial partitioning, the concept vectors are iteratively calculated to a stopping threshold value, leaving a concept vector subspace of the document vectors. The documents can then be projected onto the concept vector subspace to be represented as a linear combination of the concept vectors, thereby reducing the dimensionality of the document space.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: May 6, 2003
    Assignee: International Business Machines Corporation
    Inventors: Inderjit Singh Dhillon, Dharmendra Shantilal Modha
  • Patent number: 6511800
    Abstract: The current invention discloses novel methods for the inhibition of inducible nitric oxide synthesis (iNOS) and the production of NO. Methods of inhibiting the induction of proinflammatory cytokines are also described. Methods of treating various disease states, such as X-linked adrenoleukodystrophy, multiple sclerosis, Alzheimer's and septic shock using inhibitors of iNOS and cytokine induction are disclosed. The inhibitors include the exemplary compounds lovastatin, a sodium salt of phenylacetic acid (NaPA), FPT inhibitor II, N-acetyl cysteine (NAC), and cAMP. Methods of treating a nitric oxide or cytokine mediated disorder in a cell comprising administering a biologically effective amount of at least one induction suppressor of an inducible nitric oxide synthase or a cytokine is also described.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: January 28, 2003
    Assignees: Medical University of South Carolina, MUSC Foundation for Research Development
    Inventor: Inderjit Singh
  • Patent number: 6489879
    Abstract: An improved PTC fuse assembly is described. The PTC fuse assembly includes a PTC fuse having a PTC material. To expedite heating of the PTC material, the improved PTC fuse assembly includes a die package in thermal communication with the PTC material. The die package includes a die which is responsible generating heat once a threshold has been reached. To mount the die package to a printed circuit board, the die package includes leads. The leads are sufficiently flexible such that the heat generated by the die does not compromise performance of the PTC protection circuit.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: December 3, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Inderjit Singh, Hem Takiar, Geoffrey Cade Murray
  • Patent number: 6459143
    Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: October 1, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
  • Publication number: 20020105351
    Abstract: A bumped wafer testing setup and associated method that eliminates the need for membrane probes. The test setup includes two plates coupled together, with the first plate including openings to accommodate solder bumps contained on the bumped wafer and the second plate including a test printed circuit board insert contained therein. The test printed circuit board insert includes solder bump contacts that contact the solder bumps within the openings.
    Type: Application
    Filed: February 5, 2001
    Publication date: August 8, 2002
    Inventor: Inderjit Singh
  • Patent number: 6364089
    Abstract: The invention relates to apparatus and methods for semiconductor device handling. In one aspect, the invention relates to a rotary flipper including a wheel having a plurality of stations. A semiconductor device is placed within a first station in a first orientation. While the semiconductor device is held, the wheel portion of the rotary flipper rotates and the next station receives another semiconductor device. When the first station is in an unloading position, the semiconductor device is released. At this point, the semiconductor device is oriented in a second position. In one aspect, the semiconductor device is released into a cavity of a tape and reel. In another aspect, vacuum pressure is applied to hold the die. In one embodiment, the invention relates to a semiconductor device handling apparatus and apparatus that includes of a rotary semiconductor device flipper.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: April 2, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Inderjit Singh, Jaime A. Bayan, Hem Takiar, Ashok S. Prabhu
  • Publication number: 20010015477
    Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.
    Type: Application
    Filed: April 26, 2001
    Publication date: August 23, 2001
    Inventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
  • Patent number: 6278191
    Abstract: A bond pad sealing arrangement and method that utilizes ball bonds to protect a bond pad is described. A relatively large free air ball is formed at a distal end of a bonding wire used for ball bonding. The free air ball is pressed against a bond pad and ultrasonically welded to form a ball bond. The bonding parameters utilized during the ball bonding are selected such that excess ball material passes is squashed outward beyond the capillary tip and overflows the periphery of the bond pad thereby completely covering and sealing the bond pad. The described structure works well to protect aluminum and other bond pads that are subject to corrosion if left exposed. In one preferred arrangement the capillary used to form the ball bond includes a cavity arrangement that molds a central portion of the ball bond to form a good intermetallic bond between the bond pad and the bonding wire.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: August 21, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Inderjit Singh
  • Patent number: 6269376
    Abstract: A method, apparatus, article of manufacture, and a memory structure for clustering data points in parallel using a distributed-memory multi-processor system is disclosed. The disclosed system has particularly advantageous application to a rapid and flexible k-means computation for data mining. The method comprises the steps of dividing a set of data points into a plurality of data blocks, initializing a set of k global centroid values in each of the data blocks k initial global centroid values, performing a plurality of asynchronous processes on the data blocks, each asynchronous process assigning each data point in each data block to the closest global centroid value within each data block, computing a set of k block accumulation values from the data points assigned to the k global centroid values, and recomputing the k global centroid values from the k block accumulation values.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: July 31, 2001
    Assignee: International Business Machines Corporation
    Inventors: Inderjit Singh Dhillon, Dharmendra Shantilal Modha
  • Patent number: 6255141
    Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: July 3, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
  • Patent number: 6213378
    Abstract: An improved wire bonding capillary construction as well as a variety of improved wire bonding techniques are described. In one method aspect of the invention, the bonding parameters are controlled to prevent the creation of flash. In other aspects bonding parameters are controlled to provide high quality bonds even at relatively low bonding temperatures. By way of example, good bonding may be obtained even at room temperature and/or without preheating the bonding surface whatsoever. Other bonding parameters including bonding force, bond power and duration may also be controlled in a manner that provides good intermetallic formation between the bonding wire and the bonding surface with or without the creation of flash.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: April 10, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Inderjit Singh
  • Patent number: 6065667
    Abstract: A capillary for use in wire bonding has a wire feed bore extending from a top end of the capillary toward a capillary tip. A cavity in the capillary tip is adjacent to and contiguous with a chamfer in the wire feed bore. The cavity defines cavity walls and a recessed tip surface. The cavity can be substantially cylindrical. The recessed tip surface can be tapered relative to a horizontal axis. The portion of the capillary tip outside of the cavity defines a wedge surface which is used for wedge bonding. The cavity allows for precision small ball bonds which are strong and which have an even bonding surface distribution. The cavity molds the ball bond into a shape substantially similar to the shape of the cavity. Although there is some flash of wire metal out from the cavity, the flash is minimized and the ball bond diameter is held to a minimum by the molding effects of the cavity. The size of the ball bond is dependent only on the size of the free air ball.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: May 23, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Inderjit Singh
  • Patent number: 6031216
    Abstract: A wire bonding apparatus has a first support arrangement for supporting a first integrated circuit package component. A second support arrangement is configured to supporting a second integrated circuit package component. The second support arrangement includes at least a portion of a heating arrangement for heating certain portions of the second component. At least portions of the first support arrangement are thermally insulated from the second support arrangement such that at least certain portions of the first component may be maintained at a temperature substantially lower than the temperature of the heated portions of the second component. The apparatus may be used in method of forming a bonding wire for electrically connecting a first contact on a first integrated circuit package component to a second contact on a second integrated circuit package component. The method includes the steps of supporting and holding the first component and the second component in a desired position.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: February 29, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Inderjit Singh, Seshadri Vikram
  • Patent number: 5938105
    Abstract: An improved capillary construction that includes a cavity suitable for at least partially molding a ball bond during a ball bonding operation as well as methods for wire bonding utilizing such a capillary are described. More specifically, a distal end of a bonding wire that passes through the capillary is ultrasonically welded to a bonding surface in a manner such that the cavity molds a significant portion of the ball bond during the ball bonding operation. The described arrangement permits the bonding force applied by the bonding machine that drives the capillary to be significantly reduced or eliminated. In some embodiments, the capillary is positioned at a predetermined standoff height relative to the bonding surface. The described arrangements have numerous advantages and permits bonding to bonding surfaces that are heated to a temperatures of less than approximately 150 degrees centigrade during the ultrasonic welding step.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: August 17, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Inderjit Singh