Patents by Inventor Inderjit Singh

Inderjit Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5912019
    Abstract: Disclosed herein are compositions containing NO donors, inhibitors of iNOS induction, and endopeptidase inhibitors, and methods for their use for combating injury induced by ischemia and reperfusion following ischemic episodes.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: June 15, 1999
    Assignee: MUSC Foundation for Research Development
    Inventor: Inderjit Singh
  • Patent number: 5886393
    Abstract: An integrated circuit package assembly is disclosed herein and includes at least one integrated circuit chip having a plurality of chip input/output terminals, an arrangement for providing electrical communication between said input/output terminals and components external to said package, and an electrical inductor arrangement. The electrical inductor arrangement includes an origination terminal, a termination terminal, at least one intermediate connecting surface and a bonding wire positioned within the package. A first segment of the bonding wire is electrically connected with the origination terminal and a second segment is electrically connected with the termination terminal. Furthermore, the bonding wire has at least one intermediate point along it's length physically connected with one intermediate connecting surface. In one embodiment, the bonding wire is continuous along its length.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: March 23, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Richard Billings Merrill, Inderjit Singh
  • Patent number: 5780772
    Abstract: A method of preventing non-uniform bonding wire sweep during an encapsulating process of an integrated circuit package includes the step of forming an encapsulating material flow restricting element between two widely spaced functional bonding wires. The integrated circuit package includes an array of electrically conductive leads for electrically connecting the package to other electrical elements and an integrated circuit die having a plurality of input/output terminal pads. A plurality of functional bonding wires electrically connects certain ones of the input/output terminal pads to associated electrically conductive leads such that the functional bonding wires have a predetermined pitch which defines an approximate minimum desired spacing between adjacent functional bonding wires. The plurality of functional bonding wires includes two widely spaced functional bonding wires which are spaced apart from one another by a distance substantially greater than the predetermined minimum desired spacing.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: July 14, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Inderjit Singh, Jaime A. Bayan
  • Patent number: 5694049
    Abstract: Burn-in module 120 contains a lower socketless board 230 and an upper socketless board 240. Device sitting positions 210, or a high temperature resistant sheet 610 perform the socket functions of holding the device 400 laterally in place and routing test signals to the device 400. The lower socketless board 230 has electrical leads which carry test signals from the oven circuitry 140 to the plurality of device positions 210. The lower socketless board 230 is fastened to the upper socketless board 240 by a connector 220. If the upper socketless board 240 is modified to contain electrical leads then connector 220 may also act as an electrical connector and carry electrical signals from the lower socketless board 230 to the upper socketless board 240.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: December 2, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Inderjit Singh, Sukhbir Singh
  • Patent number: 5422892
    Abstract: A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: June 6, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Francis Hii, Inderjit Singh, James E. Rousey