Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate.

Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.

Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.

Abstract: A transparent dielectric composition comprising tin, oxygen and one of aluminum or magnesium with preferably higher than 15% by weight of aluminum or magnesium offers improved thermal stability over tin oxide with respect to appearance and optical properties under high temperature processes. For example, upon a heat treatment at temperatures higher than 500 C, changes in color and index of refraction of the present transparent dielectric composition are noticeably less than those of tin oxide films of comparable thickness. The transparent dielectric composition can be used in high transmittance, low emissivity coated panels, providing thermal stability so that there are no significant changes in the coating optical and structural properties, such as visible transmission, IR reflectance, microscopic morphological properties, color appearance, and haze characteristics, of the as-coated and heated treated products.

Abstract: A composition for removing photoresist and bottom anti-reflective coating from a semiconductor substrate is disclosed. The composition may comprise a nontoxic solvent, the nontoxic solvent having a flash point above 80 degrees Celsius and being capable of dissolving acrylic polymer and phenolic polymer. The composition may further comprise Tetramethylammonium Hydroxide (TMAH) mixed with the nontoxic solvent.

Abstract: Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are processed in series with some degrees of overlapping between regions. In some embodiments, overlapping combinatorial processing can be used in conjunction with non-overlapping combinatorial processing and non-combinatorial processing to develop and investigate materials and processes for device processing and manufacturing.

Abstract: A system and method for combinatorial processing of substrates in a processing chamber. The system includes a plurality of generators for supplying power into the processing chamber. A plurality of sputter guns provides power to different regions of a substrate. A switchbox switches power from a generator to a sputter gun via a plurality of coaxial switches. A controller positioned within the switchbox automatically distributes power from a specific generator to a specific sputter gun under programmable logic control.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

Abstract: Methods for increasing the power output of a TFPV solar panel using thin absorber layers comprise techniques for roughening and/or texturing the back contact layer. The techniques comprise roughening the substrate prior to the back contact deposition, embedding particles in sol-gel films formed on the substrate, and forming multicomponent, polycrystalline films that result in a roughened surface after a wet etch step, etc.

Abstract: A doctor blade assembly for use in combination with apparatus for forming a film on a substrate. The doctor blade assembly includes a doctor blade to be mounted on a programmable robot. The doctor blade has a bottom face and spacers at opposite ends of the body of the doctor blade extending a predetermined distance down below the bottom face of the body for contacting a substrate and spacing the bottom face from the substrate. The spacers are adjustable relative to the doctor blade for adjusting the predetermined distance according to the thickness of film to be formed on the substrate. Other aspects and methods are also disclosed.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2?x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.