Abstract: A received signal strength indicator (RSSI) receives an input voltage. The input voltage is amplified by a cascade of voltage amplifiers. The output of each amplifier is squared by a squarer. The output of each squarer is then compared to an array of fixed values from a strictly monotonic sequence. The comparators outputs are fed to a digital thermometer decoder, the outputs of which represent the binary coded, arbitrarily shaped RSSI. The squarer can be implemented using two MOS transistors, and has a current output. The comparators can be implemented using multiple current mirrors.

Abstract: According to some embodiments, an electronic circuit comprises a digital output which is held to a logic one after the power supply was removed, for a time duration in a narrow range. The electronic circuit comprises a first array of elements comprising capacitors and discharging devices (diodes or transistors). A time constant detector detects which elements has the discharging time closest to the target. A second array of elements also comprises capacitors and discharging devices, with discharging durations proportional to the discharging durations of the first array. A decoder charges the appropriate element from the second array. After the power is removed, this charged element starts to discharge. During the discharge duration, a comparator outputs a logic one, and a logic zero after the discharge is completed.

Abstract: According to some embodiments, a switch having an “on” state and an “off” state is exhibiting a low impedance in the “on” state, and a very high impedance in the “off” state. The switch comprises three series MOS transistors, the first transistor having its drain connected to the input. The switch also comprises additional circuitry which reduces, in the “off” state, the leakage current of the MOS transistor connected to the input of the switch by connecting its source and bulk to an electrical node replicating the voltage of the input node. According to some embodiments, the said switch is used in a voltage amplifier for capacitive sensing devices, such as MEMS gyroscopes and MEMS microphones; the voltage amplifier uses an operational amplifier used in a trans-capacitance configuration, with the feedback path comprising the said switch and a capacitor, wherein the said switch is connected to the input of, the voltage amplifier.

Abstract: According to some embodiments, a trans-capacitance amplifier is exhibiting an input current of the biasing in the range of picoAmperes while allowing large output swings. The trans-capacitance amplifier comprises an operational amplifier, a feedback capacitor, circuitry to DC bias and to AC ground the non-inverting input of the operational amplifier, and circuitry to DC bias the inverting input of the operational amplifier. According to some embodiments, the circuitry to bias the inverting input comprises a cascade of degenerated differential pairs. The first transistor of the first pair and the second transistor of the last pair have an active load. The cascade of differential pairs and the active load create a trans-conductance amplifier with a very low equivalent trans-conductance. According to some embodiments, the same invention applies to a differential trans-capacitance amplifier.

Abstract: According to some embodiments, a digital to analog converter comprises an array of input data streams. An array of differential MOS switches are all biased by a common tail current source. A data stream combiner combines and selects at each clock cycle the correct bit. Only one transistor from the switches conducts current at any time. The duration during which a switch conducts current is independent upon the fronts of the bits from the input data streams, thus rendering the switching code independent.

Abstract: A reconstruction circuit for the pixel clock in digital display units receiving analog display data uses a multi-phase reference clock and an all digital PLL for clock generation and synchronization to an external sync signal. A phase/frequency detector in the digital PLL uses a multi-phase reference clock to achieve a high resolution of the phase error. The digital PLL control algorithm can be implemented with a single loop and can achieved arbitrary large, externally controlled, phase difference between the generated pixel clock and the input sync signal.

Abstract: We describe an analogue optical MEMS spatial light modulator (SLM) comprising optical phase modulating MEMS pixels each with a pixel electrode and a mirror mounted on a spring such that said mirror is able to translate in a direction perpendicular to said substrate substantially without tilting, under the influence of a voltage applied to said pixel electrode. The CMOS substrate comprises an analogue pixel driver circuit for each of the pixels to apply an analogue voltage to the pixel electrode. The analogue pixel driver circuit comprises a pixel voltage input to receive an analogue voltage, a first and second sample/hold circuits coupled to the pixel voltage input, and a multiplexer having respective inputs coupled to said first and second sample/hold circuits, an output coupled to the pixel electrode, and a select line to control said multiplexer to selectively couple said first and second S/H circuits to the pixel electrode.

Abstract: We describe a method of compensating for long-term mechanical property changes in an analogue optical MEMS SLM. In embodiments the SLM comprises multiple piston-type actuation optical phase modulating pixels each having a mirror with a variable height determined by an analogue voltage applied to a corresponding pixel electrode. The method comprises performing initial calibrations of the analogue displacement and pixel capacitance versus analogue voltage to determine a relationship between the pixel capacitance and analogue displacement, and then updating the displacement-voltage capacitance using the initial calibration data and a later calibration of the analogue voltage-capacitance characteristic of a pixel.

Abstract: A self-biased electrecret microphone amplifier with phantom biasing is using only standard devices implemented in a digital Complementary Metal Oxide Semiconductor (CMOS) process. The stable gain is provided open loop with a self-biased linear transconductance amplifier device that does not require large external components for filtering.

Abstract: A system and method for signal channel balancing through accurate estimation of signal amplitude and phase parameters are described. The system includes multiple analog-to-digital (A/D) converter devices coupled to a digital signal processing (DSP) unit, each A/D converter device corresponding to a communication channel within the system. The system further includes multiple analog multiplexers, each analog multiplexer being coupled to a corresponding A/D converter device and having a number of inputs equal to the number of communication channels to be balanced within the system. The system further includes a timing generator circuit and selection logic coupled to the DSP unit, such that for each clock cycle, a single analog channel input is routed to each A/D converter device.

Abstract: A second order analog filter based on transconductance amplifiers and capacitors (gmC) has good linearity at low operating voltage by using linear active transconductance amplifiers with gains determined by physical resistors and output current mirrors in a positive feedback configuration to allow the implementation of complex poles in the transfer function.

Abstract: An analog-to-digital converter circuit and method with reduced non-linearity are described. The circuit includes an amplifier module having at least one active input coupled to at least three capacitor devices. The circuit further includes multiple switches coupled to each respective capacitor device. One switch coupled to each capacitor device is further coupled to an output of the amplifier module, such that each capacitor device can be selectively coupled to the output of the amplifier module. At least one switch coupled to each capacitor device is further coupled to a reference voltage source to receive at least one reference voltage signal. Finally, at least one switch coupled to each capacitor device is further coupled to receive an input voltage signal.

Abstract: Methods are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal.

Abstract: Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses.

Abstract: A low voltage Complementary Metal Oxide Semiconductor (CMOS) driver circuit for inductive loads is described. The circuit includes at least two first transistor devices, each first transistor device having a drain coupled to an inductive load, a respective second transistor device corresponding to each first transistor device having a drain coupled to a gate of the corresponding first transistor device, and a respective third transistor device corresponding to each first transistor device having a drain coupled to a source of the corresponding first transistor device. If a second transistor device corresponding to a first transistor device of the two first transistor devices is turned off, then a third transistor device corresponding to the remaining first transistor device is turned off, a gate of the first transistor device is floating and a drain-to-gate voltage at the first transistor device is reduced to below a predetermined supply voltage applied at a source of the respective second transistor device.

Abstract: Methods and devices perform analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal to thereby provide fairly good guesses.

Abstract: Embodiments of a variable gain amplifier circuit are described. In one embodiment, multiple resistor devices are coupled in series to form a string of resistor devices and to receive an input current. A multiple input operational amplifier device has an amplifier output coupled to a feedback resistor in the string of resistor devices and multiple amplifier input pairs, each amplifier input being coupled into the string of resistor devices as a tap between two respective adjacent resistors, each amplifier input pair being controlled by a corresponding bias current transmitted from a respective bias current source.

Abstract: An image processing system includes a charge-coupled device sensor having a wide input dynamic range, and an analog front end circuit coupled to the charge-coupled device sensor. The front end circuit includes an analog-to-digital converter module to receive an input analog signal from the charge-coupled device sensor, the analog-to-digital converter module having a signal to noise ratio corresponding to a predetermined number of bits and a higher resolution than the predetermined number of bits. The front end circuit further includes a digital multiplier module coupled to the analog-to-digital converter module, the analog-to-digital converter module and the digital multiplier module to adjust a full scale input range at the analog-to-digital converter module over the wide range without loss in analog-to-digital conversion resolution.

Abstract: A circuit for generating an output oscillation signal with low jitter includes an oscillator to generate an oscillation signal at an initial frequency based upon a control input to vary an amplitude of the oscillation signal. A first frequency multiplier multiplies the oscillation signal to result in a first signal with first frequency and first undesired frequency components. A filter minimizes the first undesired frequency components of the first signal. A second frequency multiplier multiplies the first signal to result in the output oscillation signal with second frequency and second undesired frequency components. A second feedback circuit compares a predetermined range and at least one of the first signal and the output oscillation signal to result in a reference value. A first feedback circuit varies the control input based upon a comparison between the reference value and the amplitude of the oscillation signal to minimize the second undesired frequency components.

Abstract: Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment, the base module generates signals with a controlled frequency, multiple equidistant phase, and reduced duty cycles. Frequency dividers using barrel-shifters driven by an early-late detector combined with a left/right “one hot” shift-register or driven by an early-late detector combined with up-down counter/decoder are also disclosed.