Abstract: Digital self-calibration of digital-to-digital converters includes an approach to correct for the arbitrary errors in the analog section provided that there are sufficient redundancy in the architecture. The calibration procedure is performed off-line (upon power-up or user request). The digital correction technique avoids the need of a very accurate current mirror or an extra digital-to-analog converter as a standard transfer device.

Abstract: A subcircuit including three bipolar transistors is substituted in place of a single bipolar transistor to achieve extrinsic base and emitter series resistance compensation in translinear circuits. The subcircuit substitution is applied to a Brokaw-type bandgap cell. The subcircuit substitution is applied to a current multiplier circuit, and the resulting circuit is rearranged for external control circuit efficiency. A low-voltage bandgap circuit uses an operational amplifier feedback circuit with bipolar transistors having differing emitter areas and a voltage divider to generate base voltages for a Brokaw-type bandgap cell. A proportional-to-absolute-temperature sensor circuit uses parallel two stacked bipolar transistor paths in which the bipolar transistors' emitter areas are selected to adhere to a relationship so as to provide extrinsic series base and emitter resistance compensation.

Abstract: An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.

Abstract: A strobed comparator circuit with reduced signal propagation time has a regenerative latch in which, during the reset phase of operation, its output nodes are discharged to a common potential which is close to the regenerative voltage level of the cross-coupled transistors forming such regenerative latch rather than to circuit ground. Accordingly, overall signal propagation time is reduced by the amount of reduction in charging time necessary for one of the discharged nodes to recharge above the threshold voltage of one of the cross-coupled latch transistors. Also included is an output monitoring circuit which determines whether the regenerative latch has remained in a metastable state.

Abstract: A low power reference buffer includes a new amplifier design with very large transconductance and high frequency non-dominant poles and a triple bonding scheme to a large off-chip capacitor that avoids the problems related to the lead wire inductance.

Abstract: An electrostatic discharge (ESD) protection circuit with reduced high frequency signal distortion includes an additional input shunting diode and a voltage follower amplifier. This second diode and the original input shunting diode are connected in series between the circuit node to be protected and circuit ground so as to limit the voltage level at such node during an ESD event. The voltage follower amplifier maintains a substantially constant voltage across this second diode, thereby maintaining a substantially constant diode junction capacitance. Hence, with the introduction of this additional, serially connected junction capacitance of the second diode, the nonlinear input capacitance responsible for input signal distortion is reduced, plus with a substantially constant diode junction capacitance due to the use of the voltage follower amplifier, such reduced capacitance remains substantially more constant over variations in the input signal voltage.

Abstract: A sample and hold (S/H) circuit with common mode differential signal feedback for converting single-ended signals to differential signals includes a feedback loop for the input switched capacitor circuit to ensure that the input common mode voltage for the differential amplifier is maintained at a known value during the hold phase of operation. The feedback loop consists of a three-input error amplifier which monitors the two voltages at the differential input terminals of the differential amplifier in relation to the common mode reference voltage and generates a feedback voltage which is applied to the input terminals of the input switched capacitor circuit during the hold phase of operation. If both of the differential input terminal voltages are either more negative or more positive than the common mode reference voltage then the feedback voltage generated by the error amplifier is made more positive or negative, respectively.

Abstract: A self-calibrating reversible pipeline analog to digital converting architecture configured to convert an input analog signal to an output digital signal and further to convert an input digital signal to an output analog signal is disclosed. The reversible pipeline architecture self-calibrates to compensate for adverse effects upon the linearity during signal conversion using a digital correction procedure. The same digital correction coefficients are used during both analog to digital conversion as well as during digital to analog conversion. The self-calibrating reversible converting architecture includes a reduced gain stage to create the necessary redundancy for the digital correction. Furthermore, the self-calibrating reversible converting architecture includes an overflow reduction stage to generate redundancy for the digital correction.

Abstract: A capacitor array-based, successive approximation analog-to-digital signal converter includes a capacitor array with a central coupling capacitor having a unit-value capacitance and two sets of input coupling capacitors having capacitances which are binary weighted multiples of such unit-value capacitance. During the sampling phase, the first set of input coupling capacitors is grounded while the second set of input coupling capacitors is driven by the analog input voltage. During the holding, or conversion, phase, one of the input coupling capacitors in the second set is grounded while each one of the input coupling capacitors in the first set and each one of the remaining input coupling capacitors in the second set is driven by a respective binary multiple of a fixed reference voltage, with each one of such binary multiples corresponding to one of the bits of the successive approximation result.

Abstract: A method and circuit for performing a monotonic digital calibration of a pipeline analog-to-digital (A/D) converter calibrates each stage of the pipeline A/D converter while using the actual input A/D converter of the stage then being calibrated. The digital output from the stage is converted to an analog signal (e.g., integrated) and fed back for use as the analog input to the stage. This ensures that the digital output from the stage has a symmetrical waveform and that the analog input voltage to the stage remains at the input threshold level. The remaining downstream pipeline A/D converter stages are then used to measure the levels of the binary residue voltage corresponding to the two states of the binary stage output so that appropriate calibration data can be generated and stored for use in calibrating that stage. By repeating this process for each successive upstream pipeline A/D converter stage the entire pipeline A/D converter can be calibrated to help ensure the monotonicity of its A/D conversion.

Abstract: A high speed fully differential operational amplifier with fast settling time for switched capacitor applications includes a high gain active cascode applied to the operational amplifier's input stage transistors to improve the gain, provide a higher output impedance, and thus, reduce the Miller feedback gate drain capacitance of the input stage devices. This improves the speed of the amplifier. A biasing technique is used to keep the active cascodes biased during transient overload so that settling will not be adversely affected during the recovery of the cascodes. A pair of transistors are used to feed forward a fraction of the tail current to "keep-alive" the cascode transistors. In other words, the fraction of the tail current that is fed to the source of the cascode transistors via the keep-alive transistors effectively biases the active cascodes sufficiently so that they do not turn off completely during slewing.

Abstract: An adaptive bias circuit for switched capacitor applications that compensates for temperature and process variations by maintaining a constant settling time of CMOS operational amplifiers is introduced. To this end, the adaptive bias circuit allows a dynamic trade-off between the slew-rate and the gain bandwidth product which allows the output of the operational amplifier to settle within a certain predetermined precision. A first aspect of the invention includes a current source providing a same current to a pair of transistors having different effective current densities. A resistor is coupled between the pair of transistors while from one end of the resistor, a constant bias current is drawn. In this manner, a voltage difference develops across the resistor which effectively indicates the change in the transconductance of the pair of transistors with respect to temperature and process variations.

Abstract: A differential amplifier with switched capacitor common mode feedback includes a differential telescopic cascode amplifier in which the differential output terminals are individually coupled to a common mode input bias terminal via separate feedback capacitors. During a first time period (e.g., a sampling period), the output terminals are connected together via a pair of output switches to provide a common mode output voltage in response to a common mode input bias voltage applied to the bias terminal via an input switch. An operational amplifier compares the common mode output voltage to a common mode reference voltage and, based upon the difference between such voltages, generates the common mode input bias voltage. During a second time period (e.g., a holding period), the input and output switches are all opened and the output terminals provide a differential output voltage in response to a differential input signal applied to the differential input terminals.

Abstract: In a pipelined radix 2 analog to digital converter, a method of analog residue formation uses an overflow reduction stage which takes an analog input and outputs a digital value of +2, 0, or -2 and an analog residue which is twice the analog input minus the digital output value times a reference voltage. A calibration technique allows a pipelined analog to digital converter using the overflow reduction stages to produce a corrected output requiring one addition per pipeline stage. The residue portion of the overflow reduction stage can be constructed using an operational amplifier, two capacitors, one of which has twice the capacitance of the other, and three on-off type switches. A radix 2 pipelined converter is constructed using a combination of standard 1-bit stages and overflow reduction stages. The analog residue is passed from stage to stage as an amplifier remainder as the digital codes are extracted in a pipelined analog to digital converter.

Abstract: A digital output buffer uses an RC delay line having more than one resistor and capacitor as a shaping circuit which drives an operational amplifier configured as voltage follower that drives an output load through a bond wire according to an embodiment, thereby achieving low ground and power supply bounce and nearly constant propagation delay under all process, temperature, and capacitive load variations. In another embodiment, taps from an RC delay line are used to drive a distributed MOS source follower. In yet another embodiment, taps from the RC delay line are used to drive the distributed MOS source follower while the final tap drives a rail-to-rail operational amplifier configured as a voltage follower. In that embodiment, the operational amplifier includes a fully complementary adaptive biasing structure which allows large overdrive voltages for the output devices.

Abstract: A carry look ahead circuit is implemented such that only one gate delay is incurred in calculating the carry output after the carry input becomes valid. The carry input and the carry output have opposite logical polarities. "Odd" carry look ahead stages are defined to have a positive logic carry input and a negative logic carry output, while "even" stages are defined to have a negative logic carry input and a positive logic carry output. Using "alternating polarity" in this manner simplifies the logic design of both odd and even stages. In a first embodiment, the generate and propagate computations are performed by a separate logic block. As the level of look ahead increases, the complexity of the generate and propagate block increases, but the remainder of the circuitry is unaffected. In a second embodiment, the generate and propagate signal computations are integrated into a complex gate which produces the carry output of each stage.

Abstract: An analog to digital converter stage that has a very short sampling phase settling time requirement is used in a multistage pipelined analog to digital converter with a novel clocking design. Each clock period has a sampling phase and a hold phase. According to a first aspect, the sampling phase of each clock cycle is much shorter than the hold phase. This takes advantage of the reduced sampling phase settling time requirement of the analog to digital converter stage according to the present invention, and also allows a relatively longer hold phase during each clock cycle. The analog to digital converter stage according to the present invention is implemented with an operational amplifier such that during the sampling phase, the operational amplifier does not have to settle in order for correct sampling to occur, whereas operational amplifier settling is required during the hold phase.

Abstract: A comparator produces a digital output based upon a differential input signal and hysteresis. To inject positive feedback, a second differential pair is added. This feedback pair is nominally identical to the input pair. If the comparator has recently sensed a positive input of sufficient magnitude to drive the comparator output high, switches are turned on coupling a positive hysteresis voltage to the inputs of the feedback differential pair. By coupling a fixed current differential from the second differential pair to the input differential pair, the effective switching threshold of the comparator is changed. A non-overlapping clock generator is formed so that the switches will not turn on simultaneously so as to short the hysteresis reference voltage source. The hysteresis voltage source can be centered at any voltage that does not exceed the common mode range of the input pair.