Patents by Inventor Isaac R. Nassi

Isaac R. Nassi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220229688
    Abstract: Distributed I/O virtualization includes receiving, at a first physical node in a plurality of physical nodes, an indication of a request to transfer data from an I/O device on the first physical node to a set of guest physical addresses. An operating system is executing collectively across the plurality of physical nodes. It further includes writing data from the I/O device to one or more portions of physical memory local to the first physical node. It further includes mapping the set of guest physical addresses to the written one or more portions of physical memory local to the first physical node.
    Type: Application
    Filed: January 31, 2022
    Publication date: July 21, 2022
    Inventors: Leon Dang, Keith Reynolds, Isaac R. Nassi
  • Publication number: 20220174130
    Abstract: Maintaining cache coherency in the presence of a network attached memory is disclosed. A computer system includes a plurality of physical nodes. An operating system is run collectively across the plurality of physical nodes. The physical nodes are configured to communicate with a network attached memory. Based at least in part on an operation to be performed with respect to page on a first physical node included in the plurality of physical nodes, the network attached memory is configured to receive a message. The network attached memory is configured to perform an action based at least in part on the received message.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 2, 2022
    Inventors: Isaac R. Nassi, David P. Reed
  • Patent number: 11275600
    Abstract: Distributed I/O virtualization includes receiving, at a first physical node in a plurality of physical nodes, an indication of a request to transfer data from an I/O device on the first physical node to a set of guest physical addresses. An operating system is executing collectively across the plurality of physical nodes. It further includes writing data from the I/O device to one or more portions of physical memory local to the first physical node. It further includes mapping the set of guest physical addresses to the written one or more portions of physical memory local to the first physical node.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: March 15, 2022
    Assignee: TidalScale, Inc.
    Inventors: Leon Dang, Keith Reynolds, Isaac R. Nassi
  • Patent number: 11240334
    Abstract: Maintaining cache coherency in the presence of a network attached memory is disclosed. A computer system includes a plurality of physical nodes. An operating system is run collectively across the plurality of physical nodes. The physical nodes are configured to communicate with a network attached memory. Based at least in part on an operation to be performed with respect to page on a first physical node included in the plurality of physical nodes, the network attached memory is configured to receive a message. The network attached memory is configured to perform an action based at least in part on the received message.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 1, 2022
    Assignee: TidalScale, Inc.
    Inventors: Isaac R. Nassi, David P. Reed
  • Publication number: 20220027164
    Abstract: Initializing a computing system using dormant pages includes marking a set of guest physical addresses as dormant. It further includes, for each node in a plurality of physical nodes, designating a set of real physical addresses for zeroing. An operating system is executing collectively across the physical nodes.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: David P. Reed, Isaac R. Nassi, Pete Jarvis
  • Publication number: 20210377107
    Abstract: Dynamic adaptive reconfiguration of a computing system includes receiving a request to remove a first node in a plurality of physical nodes. An operating system is executing collectively across the plurality of physical nodes, and an application is running on the operating system. It further includes in response to the request, and while the application is running, evacuating virtualized resources associated with the first node to one or more other nodes in the plurality of physical nodes. It further includes subsequent to the evacuation of the virtualized resources, removing the first node from the plurality of physical nodes.
    Type: Application
    Filed: May 14, 2021
    Publication date: December 2, 2021
    Inventors: David P. Reed, Isaac R. Nassi, Gary Smerdon
  • Patent number: 11175927
    Abstract: Initializing a computing system using dormant pages includes marking a set of guest physical addresses as dormant. It further includes, for each node in a plurality of physical nodes, designating a set of real physical addresses for zeroing. An operating system is executing collectively across the physical nodes.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 16, 2021
    Assignee: TidalScale, Inc.
    Inventors: David P. Reed, Isaac R. Nassi, Pete Jarvis
  • Patent number: 11159605
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 26, 2021
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi
  • Publication number: 20210240356
    Abstract: Handling frequently accessed pages is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is a frequently updated portion of memory. The stalling event is handled based at least in part on the determination that the requested portion of memory is a frequently updated portion of memory.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 5, 2021
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, Michael Berman, I-Chun Fang, Mark Hill, Brian Moffet, Jeffrey Paul Radick, David P. Reed, Keith Reynolds
  • Patent number: 11050620
    Abstract: Dynamic adaptive reconfiguration of a computing system includes receiving a request to remove a first node in a plurality of physical nodes. An operating system is executing collectively across the plurality of physical nodes, and an application is running on the operating system. It further includes in response to the request, and while the application is running, evacuating virtualized resources associated with the first node to one or more other nodes in the plurality of physical nodes. It further includes subsequent to the evacuation of the virtualized resources, removing the first node from the plurality of physical nodes.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 29, 2021
    Assignee: TidalScale, Inc.
    Inventors: David P. Reed, Isaac R. Nassi, Gary Smerdon
  • Patent number: 11023135
    Abstract: Handling frequently accessed pages is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is a frequently updated portion of memory. The stalling event is handled based at least in part on the determination that the requested portion of memory is a frequently updated portion of memory.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 1, 2021
    Assignee: TidalScale, Inc.
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, Michael Berman, I-Chun Fang, Mark Hill, Brian Moffet, Jeffrey Paul Radick, David P. Reed, Keith Reynolds
  • Publication number: 20210132979
    Abstract: Initializing a software-defined server having software-defined NUMA domains includes, when booting a virtual environment defined by a set of hyper-kernels running on a plurality of physically interconnected computing nodes, accessing information associated with a software-defined NUMA domain configuration. It further includes, based at least in part on the accessed information, assigning software-defined NUMA domains to computing nodes. It further includes assigning virtualized resources to the software-defined NUMA domains. Handling a stalling event involving software-defined NUMA domains includes receiving an indication that a core or hyperthread which instantiates a virtual processor cannot access a virtualized resource needed by the core or hyperthread.
    Type: Application
    Filed: October 27, 2020
    Publication date: May 6, 2021
    Inventors: Brian D. Moffet, John Houston Gray, Jeffrey Paul Radick, Charles Joseph Levine, Isaac R. Nassi
  • Publication number: 20210011777
    Abstract: Entanglement of pages and threads is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is an entangled portion of memory that is entangled with a physical node in a plurality of physical nodes. A type of the entangled portion of memory is determined. The stalling event is handled based at least in part on the determined type of the entangled portion of memory.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 14, 2021
    Inventors: Isaac R. Nassi, David P. Reed, Mark Hill
  • Patent number: 10817347
    Abstract: Entanglement of pages and threads is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is an entangled portion of memory that is entangled with a physical node in a plurality of physical nodes. A type of the entangled portion of memory is determined. The stalling event is handled based at least in part on the determined type of the entangled portion of memory.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 27, 2020
    Assignee: TidalScale, Inc.
    Inventors: Isaac R. Nassi, David P. Reed, Mark Hill
  • Patent number: 10783000
    Abstract: Associating working sets and threads is disclosed. An indication of a stalling event is received. In response to receiving the indication of the stalling event, a state of a processor associated with the stalling event is saved. At least one of an identifier of a guest thread running in the processor and a guest physical address referenced by the processor is obtained from the saved processor state.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 22, 2020
    Assignee: TidalScale, Inc.
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, David P. Reed, I-Chun Fang, Michael Berman, Mark Hill, Brian Moffet
  • Publication number: 20200192702
    Abstract: Resource migration negotiation is disclosed. A request is received, from a remote physical node in a plurality of physical nodes, for a resource. An operating system is run collectively across the plurality of physical nodes. The request includes information pertaining to a guest thread running on the remote physical node. Based at least in part on at least some of the information included in the request, it is determined whether to send the requested resource or reject the request. A response is provided based at least in part on the determination.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, Brian Moffet, Michael Berman, David P. Reed
  • Publication number: 20200186596
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Inventor: Isaac R. Nassi
  • Publication number: 20200142608
    Abstract: Hierarchical stalling strategies are disclosed. An indication is received of a stalling event caused by a requested resource being inaccessible. In response to receiving the indication of the stalling event, a set of cost functions usable to determine how to handle the stalling event is selected based at least in part on a type of the stalling event. The stalling event is handled based at least in part on an evaluation of the set of cost functions selected based at least in part on the type of the stalling event.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, Michael Berman, Mark Hill, Brian Moffet, Jeffrey Paul Radick, David P. Reed, Keith Reynolds
  • Publication number: 20200142733
    Abstract: Dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. In response to receiving an indication of an event occurring, a search is performed for a queue in a set of queues on which to place a virtual processor that had been waiting on the event. Queues in the set of queues correspond to hyperthreads in a physical node in the plurality of physical nodes. The queues in the set of queues are visited according to a predetermined traversal order.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Isaac R. Nassi, Mark Hill, I-Chun Fang, Kleoni Ioannidou
  • Patent number: 10645150
    Abstract: Hierarchical dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. An abstraction of the nodes, processors, and hyperthreads forms a hierarchy. Upon receiving an indication that a hyperthread should be assigned, a dynamic search of the hierarchy is performed, beginning at the leaf level, for a process to assign to the hyperthread.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 5, 2020
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi