Patents by Inventor Isaac R. Nassi

Isaac R. Nassi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190149399
    Abstract: Dynamic adaptive reconfiguration of a computing system includes receiving a request to remove a first node in a plurality of physical nodes. An operating system is executing collectively across the plurality of physical nodes, and an application is running on the operating system. It further includes in response to the request, and while the application is running, evacuating virtualized resources associated with the first node to one or more other nodes in the plurality of physical nodes. It further includes subsequent to the evacuation of the virtualized resources, removing the first node from the plurality of physical nodes.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 16, 2019
    Inventors: David P. Reed, Isaac R. Nassi, Gary Smerdon
  • Publication number: 20190146825
    Abstract: Distributed I/O virtualization includes receiving, at a first physical node in a plurality of physical nodes, an indication of a request to transfer data from an I/O device on the first physical node to a set of guest physical addresses. An operating system is executing collectively across the plurality of physical nodes. It further includes writing data from the I/O device to one or more portions of physical memory local to the first physical node. It further includes mapping the set of guest physical addresses to the written one or more portions of physical memory local to the first physical node.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 16, 2019
    Inventors: Leon Dang, Keith Reynolds, Isaac R. Nassi
  • Publication number: 20190146803
    Abstract: Initializing a computing system using dormant pages includes marking a set of guest physical addresses as dormant. It further includes, for each node in a plurality of physical nodes, designating a set of real physical addresses for zeroing. An operating system is executing collectively across the physical nodes.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 16, 2019
    Inventors: David P. Reed, Isaac R. Nassi, Pete Jarvis
  • Publication number: 20190065279
    Abstract: Entanglement of pages and threads is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is an entangled portion of memory that is entangled with a physical node in a plurality of physical nodes. A type of the entangled portion of memory is determined. The stalling event is handled based at least in part on the determined type of the entangled portion of memory.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 28, 2019
    Inventors: Isaac R. Nassi, David P. Reed, Mark Hill
  • Patent number: 10205772
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 12, 2019
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi
  • Patent number: 10187452
    Abstract: Hierarchical dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. An abstraction of the nodes, processors, and hyperthreads forms a hierarchy. Upon receiving an indication that a hyperthread should be assigned, a dynamic search of the hierarchy is performed, beginning at the leaf level, for a process to assign to the hyperthread.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 22, 2019
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi
  • Publication number: 20180373561
    Abstract: Hierarchical stalling strategies are disclosed. An indication is received of a stalling event caused by a requested resource being inaccessible. In response to receiving the indication of the stalling event, a set of cost functions usable to determine how to handle the stalling event is selected based at least in part on a type of the stalling event. The stalling event is handled based at least in part on an evaluation of the set of cost functions selected based at least in part on the type of the stalling event.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 27, 2018
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, Michael Berman, Mark Hill, Brian Moffet, Jeffrey Paul Radick, David P. Reed, Keith Reynolds
  • Publication number: 20180373441
    Abstract: Handling frequently accessed pages is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is a frequently updated portion of memory. The stalling event is handled based at least in part on the determination that the requested portion of memory is a frequently updated portion of memory.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 27, 2018
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, Michael Berman, I-Chun Fang, Mark Hill, Brian Moffet, Jeffrey Paul Radick, David P. Reed, Keith Reynolds
  • Publication number: 20180060121
    Abstract: Dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. In response to receiving an indication of an event occurring, a search is performed for a queue in a set of queues on which to place a virtual processor that had been waiting on the event. Queues in the set of queues correspond to hyperthreads in a physical node in the plurality of physical nodes. The queues in the set of queues are visited according to a predetermined traversal order.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Inventors: Isaac R. Nassi, Mark Hill, I-Chun Fang, Kleoni Ioannidou
  • Publication number: 20180060120
    Abstract: Resource migration negotiation is disclosed. A request is received, from a remote physical node in a plurality of physical nodes, for a resource. An operating system is run collectively across the plurality of physical nodes. The request includes information pertaining to a guest thread running on the remote physical node. Based at least in part on at least some of the information included in the request, it is determined whether to send the requested resource or reject the request. A response is provided based at least in part on the determination.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, Brian Moffet, Michael Berman, David P. Reed
  • Publication number: 20180060071
    Abstract: Associating working sets and threads is disclosed. An indication of a stalling event is received. In response to receiving the indication of the stalling event, a state of a processor associated with the stalling event is saved. At least one of an identifier of a guest thread running in the processor and a guest physical address referenced by the processor is obtained from the saved processor state.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Inventors: Isaac R. Nassi, Kleoni Ioannidou, David P. Reed, I-Chun Fang, Michael Berman, Mark Hill, Brian Moffet
  • Publication number: 20170279872
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Application
    Filed: February 10, 2017
    Publication date: September 28, 2017
    Inventor: Isaac R. Nassi
  • Publication number: 20170149921
    Abstract: Maintaining cache coherency in the presence of a network attached memory is disclosed. A computer system includes a plurality of physical nodes. An operating system is run collectively across the plurality of physical nodes. The physical nodes are configured to communicate with a network attached memory. Based at least in part on an operation to be performed with respect to page on a first physical node included in the plurality of physical nodes, the network attached memory is configured to receive a message. The network attached memory is configured to perform an action based at least in part on the received message.
    Type: Application
    Filed: September 28, 2016
    Publication date: May 25, 2017
    Inventors: Isaac R. Nassi, David P. Reed
  • Patent number: 9609048
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: March 28, 2017
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi
  • Patent number: 9191435
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 17, 2015
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi
  • Publication number: 20140059110
    Abstract: Hierarchical dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. An abstraction of the nodes, processors, and hyperthreads forms a hierarchy. Upon receiving an indication that a hyperthread should be assigned, a dynamic search of the hierarchy is performed, beginning at the leaf level, for a process to assign to the hyperthread.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 27, 2014
    Inventor: Isaac R. Nassi
  • Publication number: 20140059543
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a HyperKernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The HyperKernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 27, 2014
    Inventor: Isaac R. Nassi