Patents by Inventor Isaac R. Nassi

Isaac R. Nassi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170149921
    Abstract: Maintaining cache coherency in the presence of a network attached memory is disclosed. A computer system includes a plurality of physical nodes. An operating system is run collectively across the plurality of physical nodes. The physical nodes are configured to communicate with a network attached memory. Based at least in part on an operation to be performed with respect to page on a first physical node included in the plurality of physical nodes, the network attached memory is configured to receive a message. The network attached memory is configured to perform an action based at least in part on the received message.
    Type: Application
    Filed: September 28, 2016
    Publication date: May 25, 2017
    Inventors: Isaac R. Nassi, David P. Reed
  • Patent number: 9609048
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: March 28, 2017
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi
  • Patent number: 9191435
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a hyper-kernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The hyper-kernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 17, 2015
    Assignee: TidalScale, Inc.
    Inventor: Isaac R. Nassi
  • Publication number: 20140059110
    Abstract: Hierarchical dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. An abstraction of the nodes, processors, and hyperthreads forms a hierarchy. Upon receiving an indication that a hyperthread should be assigned, a dynamic search of the hierarchy is performed, beginning at the leaf level, for a process to assign to the hyperthread.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 27, 2014
    Inventor: Isaac R. Nassi
  • Publication number: 20140059543
    Abstract: Selective resource migration is disclosed. A computer system includes physical memory and a plurality of physical processors. Each of the processors has one or more cores and each core instantiates one or more virtual processors that executes program code. Each core is configured to invoke a HyperKernel on its hosting physical processor when the core cannot access a portion of the physical memory needed by the core. The HyperKernel selectively moves the needed memory closer to a location accessible by the physical processor or remaps the virtual processor to another core.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 27, 2014
    Inventor: Isaac R. Nassi