Patents by Inventor Isao Obu

Isao Obu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10594271
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 17, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Publication number: 20200066886
    Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 27, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Takayuki TSUTSUI, Satoshi TANAKA
  • Publication number: 20200052663
    Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 13, 2020
    Inventors: Shigeki KOYA, Yasunari UMEMOTO, Yuichi SAITO, Isao OBU, Takayuki TSUTSUI
  • Publication number: 20200027876
    Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 23, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Shigeki KOYA, Yasunari UMEMOTO, Takayuki TSUTSUI
  • Publication number: 20200027805
    Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA
  • Publication number: 20200006265
    Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Kazuya KOBAYASHI, Atsushi KUROKAWA, Hiroaki TOKUYA, Isao OBU, Yuichi SAITO
  • Publication number: 20190386122
    Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Isao OBU, Kaoru IDENO, Shigeki KOYA
  • Patent number: 10475717
    Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: November 12, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
  • Publication number: 20190326191
    Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 24, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Isao OBU, Yasunari UMEMOTO, Yasuhisa YAMAMOTO, Masahiro SHIBATA, Takayuki TSUTSUI
  • Publication number: 20190296699
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 26, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
  • Patent number: 10374071
    Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, an emitter layer, and a semiconductor layer that are laminated in this order, wherein the emitter layer includes a first region having an upper surface on which the semiconductor layer is laminated, and a second region being adjacent to the first region and having an upper surface that is exposed, and the first and second regions of the emitter layer have higher doping concentrations in portions near the upper surfaces than in portions near an interface between the emitter layer and the base layer.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 6, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari Umemoto, Shigeki Koya, Shigeru Yoshida, Isao Obu
  • Patent number: 10361666
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 23, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Patent number: 10355114
    Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 16, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Shigeru Yoshida, Masahiro Shibata
  • Publication number: 20190198464
    Abstract: A plurality of unit transistors that are connected in parallel to each other are formed on a substrate. In addition, a ground bump is provided on the substrate. A plurality of first capacitors are each provided for a corresponding one of the plurality of unit transistors and each connect an output electrode of the corresponding one of the plurality of unit transistors and the ground bump to each other.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 27, 2019
    Inventors: Takayuki TSUTSUI, Isao OBU
  • Publication number: 20190190476
    Abstract: A power amplifier circuit includes a first transistor amplifying a first signal; a second transistor amplifying a second signal; a bias circuit supplying a bias current or voltage to a base or gate of the second transistor; and an attenuator attenuating the first or second signal in accordance with a control voltage supplied from the bias circuit. The attenuator includes a first diode to which the control voltage is supplied, a third transistor including a collector connected to a supply path of the first or second signal, an emitter connected to a ground, and a base to which the control voltage is supplied from the first diode, and a capacitor connected in parallel with the first diode. The control voltage decreases as a second signal power level increases. The third transistor allows part of the first or second signal to pass to the emitter in accordance with the control voltage.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 20, 2019
    Inventors: Masao KONDO, Satoshi TANAKA, Yasuhisa YAMAMOTO, Takayuki TSUTSUI, Isao OBU
  • Publication number: 20190190455
    Abstract: A transmission unit includes a first transistor that amplifies power of a first signal and outputs a second signal, a power supply circuit that supplies to the first transistor a power supply voltage that changes in accordance with an amplitude level of the first signal, and an attenuator that attenuates the first signal in such a manner that an amount of attenuation of the first signal increases with a decrease in the power supply voltage when the power supply voltage is less than a first level.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 20, 2019
    Inventors: Masao KONDO, Satoshi TANAKA, Yasuhisa YAMAMOTO, Takayuki TSUTSUI, Isao OBU
  • Publication number: 20190172933
    Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 6, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Publication number: 20190158044
    Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 23, 2019
    Inventors: Isao OBU, Satoshi TANAKA, Takayuki TSUTSUI, Yasunari UMEMOTO
  • Publication number: 20190158039
    Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Inventors: Shigeki Koya, Takayuki Tsutsui, Yasunari Umemoto, Isao Obu, Satoshi Tanaka
  • Publication number: 20190115338
    Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Takayuki TSUTSUI, Isao OBU, Yasuhisa YAMAMOTO