Abstract: A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract: A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first base layer and a second base layer the first base layer forming a heterojunction with the collector layer and being composed of a semiconductor containing a material as a main component, the material being lattice-mismatched to the main component of the collector layer, the first base layer having a film thickness less than a critical thickness at which a misfit dislocation is introduced, the second base layer being joined to the first base layer and composed of a semiconductor containing a material as a main component, and the material being lattice-matched to the main component of the collector layer; and an emitter layer that forms a heterojunction with the second base layer.

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract: A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first base layer and a second base layer the first base layer forming a heterojunction with the collector layer and being composed of a semiconductor containing a material as a main component, the material being lattice-mismatched to the main component of the collector layer, the first base layer having a film thickness less than a critical thickness at which a misfit dislocation is introduced, the second base layer being joined to the first base layer and composed of a semiconductor containing a material as a main component, and the material being lattice-matched to the main component of the collector layer; and an emitter layer that forms a heterojunction with the second base layer.

Abstract: A heterojunction bipolar transistor includes a ballast resistor layer of which resistance increases with an increase in temperature. The ballast resistor layer includes a first ballast resistor sub-layer having a positive temperature coefficient of resistivity in a first temperature range and a second temperature range and a second ballast resistor sub-layer having a negative temperature coefficient of resistivity in the first temperature range and a positive temperature coefficient of resistivity in the second temperature range.

Abstract: A heterojunction bipolar transistor includes a ballast resistor layer of which resistance increases with an increase in temperature. The ballast resistor layer includes a first ballast resistor sub-layer having a positive temperature coefficient of resistivity in a first temperature range and a second temperature range and a second ballast resistor sub-layer having a negative temperature coefficient of resistivity in the first temperature range and a positive temperature coefficient of resistivity in the second temperature range.

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract: In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.

Abstract: The present invention provides a semiconductor device that includes a plurality of transistor cells and makes it possible to achieve higher degree of integration and lower cost of an integrated semiconductor circuit device as the first object, and provide an integrated semiconductor circuit device of high density integration and compact construction at a low cost.

Abstract: A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.