Patents by Inventor Isao Suzumura

Isao Suzumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240421159
    Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Inventors: Isao SUZUMURA, Kazufumi WATABE, Yoshinori ISHII, Hidekazu MIYAKE, Yohei YAMAGUCHI
  • Patent number: 12166131
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 10, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Tomoyuki Ito, Toshihide Jinnai, Isao Suzumura, Akihiro Hanada, Ryo Onodera
  • Patent number: 12159876
    Abstract: The purpose of the present invention is to decrease the resistance of the drain and source in the TFT of the oxide semiconductor as well as to have stable Vd-Id characteristics of the TFT. The structure of the present invention is as follows: A display device having plural pixels including thin film transistors (TFT) having oxide semiconductor films comprising: a gate insulating film formed on the oxide semiconductor film, an aluminum oxide film formed on the gate insulating film, a gate electrode formed on the aluminum oxide film, a side spacer formed on both sides of the gate electrode, and an interlayer insulating film formed on the gate electrode, the side spacer, a drain and a source, wherein in a plan view, and in a direction from the drain to the source, a length of the gate electrode is shorter than a length of the aluminum oxide film.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: December 3, 2024
    Assignee: Japan Display Inc.
    Inventor: Isao Suzumura
  • Publication number: 20240369891
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI, Isao SUZUMURA, Hajime WATAKABE, Ryo ONODERA
  • Patent number: 12127417
    Abstract: According to one embodiment, a sensor device includes an insulating base including a meandering strip-shaped portion and an island-shaped portion, a first inorganic insulating film on the island-shaped portion, a first wiring layer on the first inorganic insulating film, a second inorganic insulating film on the first wiring layer, a second wiring layer on the second inorganic insulating film, an organic insulating film on the second wiring layer, a barrier film covering the organic insulating film, a sensor element on the barrier film, and a sealing film covering the sensor element. The barrier film covers side surfaces of the organic insulating film, and the sealing film is in contact with the barrier film and the second inorganic insulating film.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: October 22, 2024
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Takumi Sano
  • Patent number: 12100709
    Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Grant
    Filed: October 4, 2023
    Date of Patent: September 24, 2024
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
  • Patent number: 12085823
    Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: September 10, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Toshihide Jinnai, Hajime Watakabe, Akihiro Hanada, Ryo Onodera, Isao Suzumura
  • Patent number: 12072595
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: August 27, 2024
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Toshihide Jinnai, Isao Suzumura, Hajime Watakabe, Ryo Onodera
  • Publication number: 20240272496
    Abstract: A display device is provided and includes a substrate on which a TFT is formed. The display device including an organic film formed on the TFT, the organic film having a through hole, and a first common electrode, an upper pixel electrode and a second common electrode which are stacked in this order above the organic passivation film, a filler being filled in the through hole, and wherein the upper pixel electrode is electrically connected with the TFT, and an edge of the upper pixel electrode is located directly on the filler.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 15, 2024
    Inventors: Fumiya KIMURA, Isao SUZUMURA
  • Publication number: 20240184177
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.
    Type: Application
    Filed: January 31, 2024
    Publication date: June 6, 2024
    Applicant: Japan Display Inc.
    Inventors: Yohei YAMAGUCHI, Arichika ISHIDA, Hidekazu MIYAKE, Hiroto MIYAKE, Isao SUZUMURA
  • Publication number: 20240142836
    Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Japan Display Inc.
    Inventors: Isao SUZUMURA, Fumiya KIMURA, Kazuhide MOCHIZUKI, Hitoshi TANAKA, Kenichi AKUTSU, Atsuko SHIMADA
  • Patent number: 11966131
    Abstract: A display device is provided and includes a substrate on which a TFT is formed. The display device including an organic film formed on the TFT, the organic film having a through hole, and a first common electrode, an upper pixel electrode and a second common electrode which are stacked in this order above the organic passivation film, a filler being filled in the through hole, and wherein the upper pixel electrode is electrically connected with the TFT, and an edge of the upper pixel electrode is located directly on the filler.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: April 23, 2024
    Assignee: Japan Display Inc.
    Inventors: Fumiya Kimura, Isao Suzumura
  • Publication number: 20240088192
    Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Akihiro HANADA, Marina MOCHIZUKI, Ryo ONODERA, Fumiya KIMURA, Isao SUZUMURA
  • Patent number: 11921392
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
  • Publication number: 20240069400
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI, Isao SUZUMURA, Hajime WATAKABE, Ryo ONODERA
  • Patent number: 11906862
    Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: February 20, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Isao Suzumura, Fumiya Kimura, Kazuhide Mochizuki, Hitoshi Tanaka, Kenichi Akutsu, Atsuko Shimada
  • Publication number: 20240030226
    Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Application
    Filed: October 4, 2023
    Publication date: January 25, 2024
    Inventors: Isao SUZUMURA, Kazufumi WATABE, Yoshinori ISHII, Hidekazu MIYAKE, Yohei YAMAGUCHI
  • Patent number: 11874574
    Abstract: According to one embodiment, a display device includes a signal line, a scanning line, a semiconductor layer, a first insulating layer which covers the semiconductor layer, a color filter above the first insulating layer, a pixel electrode above the color filter and a common electrode. The first insulating layer includes a first contact hole for connecting the semiconductor layer and the pixel electrode to each other. The first contact hole is provided at a position displaced from the color filter in plan view.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: January 16, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Fumiya Kimura, Isao Suzumura
  • Patent number: 11855117
    Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 26, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Akihiro Hanada, Marina Mochizuki, Ryo Onodera, Fumiya Kimura, Isao Suzumura
  • Publication number: 20230411401
    Abstract: The purpose of the present invention is to decrease the resistance of the drain and source in the TFT of the oxide semiconductor as well as to have stable Vd-Id characteristics of the TFT. The structure of the present invention is as follows: A display device having plural pixels including thin film transistors (TFT) having oxide semiconductor films comprising: a gate insulating film formed on the oxide semiconductor film, an aluminum oxide film formed on the gate insulating film, a gate electrode formed on the aluminum oxide film, a side spacer formed on both sides of the gate electrode, and an interlayer insulating film formed on the gate electrode, the side spacer, a drain and a source, wherein in a plan view, and in a direction from the drain to the source, a length of the gate electrode is shorter than a length of the aluminum oxide film.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventor: Isao SUZUMURA