Patents by Inventor Isao Suzumura
Isao Suzumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180286890Abstract: The purpose of the invention is to improve reliability of the TFT of the oxide semiconductor. The invention is characterized as follows. A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor; a first gate insulating film is formed on the first oxide semiconductor, a gate electrode is formed on the first gate insulating film, an interlayer insulating film is formed over the gate electrode; the gate insulating film includes a first silicon oxide film, the gate electrode includes a first gate layer made of a second oxide semiconductor and a second gate layer made of metal or alloy; the interlayer insulating film has a first interlayer insulating film including a second silicon oxide film, and a second interlayer insulating film including a first aluminum oxide film on the first interlayer insulating film.Type: ApplicationFiled: March 16, 2018Publication date: October 4, 2018Applicant: Japan Display Inc.Inventors: Isao Suzumura, Yohei Yamaguchi, Hajime Watakabe, Akihiro Hanada, Hirokazu Watanabe, Marina Shiokawa
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Publication number: 20180286888Abstract: The purpose of the present invention is to realize the TFT of the oxide semiconductor having a superior characteristics and high reliability during the product's life. The structure of the present invention is as follows. A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor, a first gate insulating film is formed on the first oxide semiconductor, the first gate insulating film is a laminated film of a first silicon oxide film and a first aluminum oxide film, a gate electrode is formed on the first aluminum film.Type: ApplicationFiled: February 9, 2018Publication date: October 4, 2018Applicant: Japan Display Inc.Inventors: Yohei Yamaguchi, Isao Suzumura
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Patent number: 10088728Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.Type: GrantFiled: July 28, 2017Date of Patent: October 2, 2018Assignee: Japan Display Inc.Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
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Publication number: 20180226498Abstract: A semiconductor device including a first oxide insulating layer, a barrier layer above the first oxide insulating layer, the barrier layer including an opening, a second oxide insulating layer above the first oxide insulating layer at a position overlapping the opening, an oxide semiconductor layer facing the first oxide insulating layer interposed by the second oxide insulating layer at a position overlapping the opening, a gate electrode facing the oxide semiconductor layer at side opposite to the first oxide insulating layer with respect to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. A contained amount of oxygen in the first oxide insulating layer is larger than a contained amount of oxygen in the second oxide insulating layer.Type: ApplicationFiled: January 26, 2018Publication date: August 9, 2018Inventors: Toshinari SASAKI, Masahiro Watabe, Masayoshi Fuchi, Isao Suzumura, Marina Shiokawa
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Patent number: 10026754Abstract: The object of the present invention is to make it possible to form an LIPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.Type: GrantFiled: May 3, 2017Date of Patent: July 17, 2018Assignee: Japan Dispaly Inc.Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
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Patent number: 9964824Abstract: According to one embodiment, a display device includes a TFT on an insulating substrate. The TFT includes a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and a source electrode and a drain electrode each provided in contact with at least a part of the semiconductor layer. The source and drain electrodes have a laminated structure including a lower layer, an intermediate layer and an upper layer. The source and drain electrodes include sidewalls each including a first tapered portion on the upper layer side, a second tapered portion on the lower layer side and a sidewall protective film attached to the second tapered portion. The taper angle of the first tapered portion is smaller than that of the second tapered portion.Type: GrantFiled: July 7, 2015Date of Patent: May 8, 2018Assignee: Japan Display Inc.Inventors: Isao Suzumura, Arichika Ishida, Norihiro Uemura, Hidekazu Miyake, Hiroto Miyake, Yohei Yamaguchi
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Publication number: 20180122835Abstract: A display device comprising: a first TFT using silicon (Si) and a second TFT using oxide semiconductor are formed on a substrate, a distance between the silicon (Si) and the substrate is smaller than a distance between the oxide semiconductor and the substrate, a drain source electrode of the first TFT connects with the silicon (Si) via a first through hole, a drain source electrode of the second TFT connects with the oxide semiconductor via a second through hole, metal films are made on the oxide semiconductor sandwiching a channel of the oxide semiconductor in a plan view, the channel has a channel width, an ALO layer is formed on the metal films and the oxide semiconductor, the second source drain electrode and the metal films are connected via the second through hole formed in the AlO layer.Type: ApplicationFiled: October 3, 2017Publication date: May 3, 2018Inventors: Hajime WATAKABE, Isao SUZUMURA, Hirokazu WATANABE, Akihiro HANADA
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Patent number: 9947798Abstract: According to one embodiment, a display device includes thin-film transistor. The thin-film transistor includes a first semiconductor layer, a first insulating film, a gate electrode, a second insulating film, a second semiconductor layer, a first electrode and a second electrode. The gap between the bottom surface of the gate electrode and the upper surface of the first channel region of the first semiconductor layer is larger than the gap between the upper surface of the gate electrode and the bottom surface of the second channel region of the second semiconductor layer.Type: GrantFiled: July 21, 2015Date of Patent: April 17, 2018Assignee: Japan Display Inc.Inventors: Hidekazu Miyake, Arichika Ishida, Norihiro Uemura, Hiroto Miyake, Isao Suzumura, Yohei Yamaguchi
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Publication number: 20180076239Abstract: The purpose of the present invention is to form both LTPS TFT and Ply-Si TFT on a same substrate. The feature of the display device to realize the above purpose is that: a display device comprising: a substrate including a first TFT having an oxide semiconductor layer and a second TFT having a Poly-Si layer, an undercoat is formed on the substrate, the oxide semiconductor layer is formed on or above the undercoat, a first interlayer insulating film is formed on or above the oxide semiconductor layer, the Poly-Si layer is formed on or above the first interlayer insulating film.Type: ApplicationFiled: August 16, 2017Publication date: March 15, 2018Inventors: Isao SUZUMURA, Hajime Watakabe, Akihiro Hanada, Hirokazu Watanabe
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Publication number: 20170343845Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.Type: ApplicationFiled: July 28, 2017Publication date: November 30, 2017Applicant: Japan Display Inc.Inventors: Yohei YAMAGUCHI, Arichika ISHIDA, Hidekazu MIYAKE, Hiroto MIYAKE, Isao SUZUMURA
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Publication number: 20170338433Abstract: An organic EL display device has a TFT formed on the substrate, and an organic EL layer formed on the TFT. A protective layer is formed on the organic EL layer, and a first bather layer which contains AlOx is formed between the substrate and the TFT.Type: ApplicationFiled: April 3, 2017Publication date: November 23, 2017Inventors: Yoshinori ISHII, Kazufumi WATABE, Isao SUZUMURA
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Publication number: 20170338249Abstract: The object of the present invention is to make it possible to form an LIPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.Type: ApplicationFiled: May 3, 2017Publication date: November 23, 2017Inventors: Isao SUZUMURA, Kazufumi WATABE, Yoshinori ISHII, Hidekazu MIYAKE, Yohei YAMAGUCHI
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Patent number: 9818881Abstract: A semiconductor device includes an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first barrier layer below the oxide semiconductor layer, and a second barrier layer above the oxide semiconductor layer, the second barrier layer covering a top surface and side surfaces of the oxide semiconductor layer and being in contact with the first barrier layer in a region around the oxide semiconductor layer.Type: GrantFiled: August 8, 2016Date of Patent: November 14, 2017Assignee: Japan Display Inc.Inventors: Toshinari Sasaki, Isao Suzumura
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Publication number: 20170323906Abstract: The invention allows formation of LTPS TFTs and TAOS TFTs on the same substrate. The invention provides a display device including a substrate having a display area in which pixels are formed. The pixels include a first TFT made of a TAOS. The drain of the first TFT is formed of first LTPS 112. The source of the first TFT is formed of second LTPS 113. The first LTPS 112 is connected to a first electrode 106 via a first through-hole 108 formed in an insulating film 105 covering the first TFT. The second LTPS 113 is connected to a second electrode 107 via a second through-hole 108 formed in the insulating film 105 covering the first TFT.Type: ApplicationFiled: April 5, 2017Publication date: November 9, 2017Inventors: Yohei YAMAGUCHI, Isao SUZUMURA, Hidekazu MIYAKE
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Patent number: 9812578Abstract: A thin film transistor includes, an insulating substrate, a gate electrode provided on an upper surface of the insulating substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer provided on the gate insulating film, a channel protective layer provided at least on an upper surface of the oxide semiconductor layer, and a source electrode and a drain electrode provided so as to come into contact with the oxide semiconductor layer, wherein the channel protective layer is formed such that the film density of a portion provided so as to come into contact with the oxide semiconductor layer is higher than the film density of a portion distant from the oxide semiconductor layer.Type: GrantFiled: October 22, 2015Date of Patent: November 7, 2017Assignee: Japan Display Inc.Inventors: Norihiro Uemura, Takeshi Noda, Hidekazu Miyake, Isao Suzumura
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Patent number: 9772536Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.Type: GrantFiled: February 28, 2017Date of Patent: September 26, 2017Assignee: JAPAN DISPLAY INC.Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
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Patent number: 9709853Abstract: To maintain good operation of a peripheral circuit using an oxide thin film transistor in a liquid crystal display panel to which photo alignment is applied, the liquid crystal display panel includes: a transparent substrate provided with an oxide thin film transistor in the periphery of a pixel portion in which pixel electrodes are arranged, to control the pixel electrodes; and an alignment film to align liquid crystal provided in the pixel portion. The alignment film is subjected to photo alignment treatment by ultraviolet irradiation. Further, an ultraviolet absorbing layer is provided so as to cover the oxide thin film transistor. For example, an alignment film is used for the ultraviolet absorbing layer to absorb the ultraviolet light for the photo aliment treatment of the alignment film, in the peripheral circuit portion for controlling the pixel electrodes, thereby preventing the threshold voltage of the oxide thin film transistor from shifting.Type: GrantFiled: September 9, 2014Date of Patent: July 18, 2017Assignee: Japan Display Inc.Inventors: Norihiro Uemura, Hidekazu Miyake, Isao Suzumura, Yohei Yamaguchi, Toshiki Kaneko
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Publication number: 20170168334Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Applicant: Japan Display Inc.Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
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Patent number: 9660039Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 ?m and less than or equal to 30 ?m. The source line and the drain line extend in directions different from each other.Type: GrantFiled: March 7, 2016Date of Patent: May 23, 2017Assignee: Japan Display Inc.Inventors: Hidekazu Miyake, Arichika Ishida, Hiroto Miyake, Isao Suzumura, Yohei Yamaguchi
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Patent number: 9620526Abstract: There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.Type: GrantFiled: February 4, 2016Date of Patent: April 11, 2017Assignee: Japan Display Inc.Inventors: Isao Suzumura, Norihiro Uemura, Hidekazu Miyake, Yohei Yamaguchi