Patents by Inventor Isao Yoshida

Isao Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050003573
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Application
    Filed: July 26, 2004
    Publication date: January 6, 2005
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Patent number: 6825548
    Abstract: It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toru Fujioka, Isao Yoshida, Toshihiko Shimizu
  • Patent number: 6815707
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Patent number: 6797594
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: September 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Publication number: 20040170865
    Abstract: A novel sub-structure of a thick film dielectric electroluminescent display and a thick film dielectric electroluminescent display incorporating the same is provided. The sub-structure comprises a barrier layer between a substrate and a thick film dielectric layer. The barrier layer is chemically inert with respect to the substrate and the thick film dielectric layer and the barrier layer inhibits diffusion of at least one chemical species therethrough. This sub-structure results in a higher capacitance for the thick dielectric layer, which provides higher display luminance and a reduced tendency for dielectric breakdown of the thick dielectric layer. The barrier layer permits for lower cost substrates, such as glass, to be used.
    Type: Application
    Filed: December 15, 2003
    Publication date: September 2, 2004
    Inventors: Hiroki Hamada, Isao Yoshida, J. Seale Daniel, Hui Zhang, Yang Maizhi, Ye Yufeng, Li Wu, M. Smy William
  • Publication number: 20040145034
    Abstract: A semiconductor device for amplification with enhanced performance is provided for use at a base station. The semiconductor device has a semiconductor chip for amplification and a transmission line substrate in the package of an amplifier used at a base station for mobile communication equipment such as a mobile phone. Stubs formed in the empty region of the transmission line substrate are connected to an output of the semiconductor chip for amplification by using bonding wires. The stubs and the bonding wires have been designed to form a resonant circuit resonating at a frequency double the fundamental frequency of an output signal from the semiconductor chip for amplification. This suppresses a doubled-frequency-wave signal of the signal outputted from the semiconductor chip for amplification and achieves an improvement in the transmission efficiency of the amplifier and a reduction in transmission distortion.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 29, 2004
    Inventors: Toru Fujioka, Toshihiko Shimizu, Isao Yoshida, Mamoru Ito, Koji Odaira, Tetsuya Iida
  • Publication number: 20040053171
    Abstract: The present invention provides a chemical amplification type positive resist composition comprising
    Type: Application
    Filed: September 9, 2003
    Publication date: March 18, 2004
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Yoshiyuki Takata, Isao Yoshida, Hirotoshi Nakanishi
  • Patent number: 6707102
    Abstract: A power MOSFET for a high frequency amplification element having good output power characteristics and high frequency characteristics is described. In the power MOSFET, a shield conductive film electrically connected to via an insulating film is arranged over a drain-offset semiconductor region. A wiring for a drain electrode is so arranged as to extent in parallel to the shield conductive film at one end side of the shield conductive film. On the other hand, a wiring for the gate electrode, a wiring for a source electrode and a gate shunt wiring are arranged in this order to extend in parallel to each other at the other end side of the shield conductive film. The shield conductive film is so formed that the thickness thereof is smaller than that of the wiring for the gate electrode. In this way, the input and output capacitances of the MOSFET can be decreased.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: March 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Morikawa, Mio Shindo, Isao Yoshida, Kenichi Nagura
  • Publication number: 20040013906
    Abstract: A thin film phosphor for an electroluminescent device, the phosphor being selected from the group consisting of thioaluminates, thiogallates and thioindates having at least one cation selected from elements of Groups IIA and IIB of the Periodic Table of Elements. The phosphor being activated by a rare earth metal and containing oxygen as a partial substitute for a portion of the sulphur in the crystal lattice of the thiogallate, thioindate or thioaluminate. The phosphor is a single phase homogeneous compound and provides improved luminance stability. An electroluminescent device comprising the thin film phosphor is also described and methods of making the phosphor of the invention.
    Type: Application
    Filed: April 17, 2003
    Publication date: January 22, 2004
    Inventors: James Alexander Robert Stiles, John Wesley Moore, Vincent Joseph Alfred Pugliese, Hiroki Hamada, Isao Yoshida
  • Publication number: 20040000676
    Abstract: It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.
    Type: Application
    Filed: June 6, 2003
    Publication date: January 1, 2004
    Inventors: Toru Fujioka, Isao Yoshida, Toshihiko Shimizu
  • Patent number: 6624257
    Abstract: A method of quantifying the protection ratio of a hydroxyl group of a polymer compound, comprising calculating the protection ratio of a hydroxyl group of a polymer compound using a multiple regression calibration curve obtained by regression-analyzing main components of near infrared absorption spectra of a plurality of standards samples, from near infrared absorption spectra of samples containing a polymer compound composed of the following first structural unit and second structural unit: first structural unit: a structural unit of a structure having a hydroxyl group, second structural unit: a structural unit of a structure obtained by introducing a protective group into a hydroxyl group in the first structural unit. By this method, the protection ratio of a hydroxyl group of the polymer compound contained in a sample can be quantified with high precision in a short period of time without isolating the polymer compound.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: September 23, 2003
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masami Yoshida, Isao Yoshida, Satoshi Yamaguchi
  • Publication number: 20030151304
    Abstract: A structure for standardizing at least one kind of part of a roller assembly for a construction vehicle so that the part can be used for a same size of construction vehicles having different structural specifications of a plurality of construction vehicle makers. The at least one kind of part includes at least one of a shell, a shaft, a floating seal, a bushing and a collar. Structural specifications including the configuration and dimension, the kind of steel or material, and the heat treatment specification or the mechanical property for the at least one kind of part are unified as much as possible over the same size of the construction vehicles of a plurality of construction vehicle makers.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 14, 2003
    Applicant: TOPY KOGYO KABUSHIKI KAISHA
    Inventors: Hiroyuki Takeno, Isao Yoshida, Makoto Takagi, Go Morishima
  • Patent number: 6605842
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: August 12, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Publication number: 20030104312
    Abstract: A chemical amplification type positive resist composition showing a high transmittance at a wavelength of 157 nm and manifesting excellent balance of abilities is provided which comprises a resin having polymerization units of the general formulae (I) and (II) and insoluble or poorly soluble itself in an alkali aqueous solution but becoming soluble in an alkali aqueous solution by the action of an acid; and an acid generating agent: 1
    Type: Application
    Filed: September 26, 2002
    Publication date: June 5, 2003
    Inventors: Yoshiko Miya, Yasunori Uetani, Satoshi Yamaguchi, Isao Yoshida
  • Publication number: 20030062537
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 3, 2003
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Patent number: 6535069
    Abstract: A radio frequency power amplifier module for a dual-band type mobile communication apparatus that can transmit and receive a first frequency f1 and second frequency f2 (f2=2×f1). It includes a drive stage amplifier having the gain peaks at f1 and f2 with a matching circuit and a radio frequency power output circuit including a radio frequency power output transistor. The output circuit has a transmission line connected to the drain end of the output transistor, a parallel resonance circuit connected in series to the transmission line to resonate at harmonics of a frequency twice the frequency f2, a series resonance circuit provided between one end of the resonance circuit and the ground to resonate at harmonics of a frequency twice the frequency f2 and an output matching circuit provided in series to the other end of the parallel resonance circuit for matching with f1 and f2.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 18, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toru Fujioka, Isao Yoshida, Mineo Katsueda, Masatoshi Morikawa, Yoshikuni Matsunaga, Kenji Sekine, Osamu Kagaya
  • Patent number: 6528848
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: March 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Patent number: 6529231
    Abstract: In a television meeting system, image data and voice data are transmitted and received among a plurality of terminal units. The terminal unit transmits and receives a video signal synthesized by combining desired background data selected by a user with taken-out image and voice. The terminal unit includes a recorder in which desired background data selected by the user is preliminarily recorded.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: March 4, 2003
    Assignee: NEC Corporation
    Inventor: Isao Yoshida
  • Patent number: 6513267
    Abstract: A snow removing machine equipped with a snow removing plate is disclosed. The snow removing plate is mounted to a front portion of a vehicle body which forms part of the snow removing machine. An operating handle having grip portions is mounted to a rear portion of the vehicle body and obliquely extends upward. A battery, an electric motor and a power transmission mechanism are located below a linear line intersecting between an upper end of the snow removing plate and the grip portion. This causes the battery, the electric motor and the power transmission mechanism to be located below a view line of an operator when he looks at the snow removing plate, avoiding the view line from being disturbed to allow the operator to look at the upper end of the snow removing plate in his working attitude for thereby providing ease of operation of the snow removing machine.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: February 4, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Isao Yoshida, Masakatsu Kono
  • Patent number: 6499236
    Abstract: A snow removing machine has a vehicle body having a body frame, a snow removing section mounted on a front portion of the body frame for removing snow, an operating handle mounted to a rear portion of the body frame and having a first handle portion and a second handle portion, and a pair of grip portions each mounted on a respective one of the first and second handle portions of the operating handle. A forward and aft drive changeover switch is directly mounted on the first handle portion of the operating handle for changing over a traveling direction of the vehicle body. A height control operation lever is directly mounted on the first handle portion of the operating handle for adjusting a height of the snow removing section. A speed control operation lever is directly mounted on the second handle portion of the operating handle for adjusting a traveling speed of the vehicle body.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: December 31, 2002
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Isao Yoshida, Yasunori Yamamoto, Norikazu Shimizu, Seishu Sakai, Masakatsu Kono