Patents by Inventor Isik C. Kizilyalli

Isik C. Kizilyalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566439
    Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 18, 2020
    Assignee: NEXGEN POWER SYSTEMS, INC.
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Publication number: 20190348522
    Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
    Type: Application
    Filed: May 28, 2019
    Publication date: November 14, 2019
    Applicant: NEXGEN POWER SYSTEMS, INC.
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Patent number: 10347736
    Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Nexgen Power Systems, Inc.
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Publication number: 20180240928
    Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Brendan M. KAYES, Hui NIE, Isik C. KIZILYALLI
  • Publication number: 20180166556
    Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
    Type: Application
    Filed: September 6, 2017
    Publication date: June 14, 2018
    Applicant: Nexgen Power Systems, Inc.
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Patent number: 9954131
    Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: April 24, 2018
    Assignee: ALTA DEVICES, INC.
    Inventors: Brendan M. Kayes, Hui Nie, Isik C. Kizilyalli
  • Publication number: 20170323987
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Hui NIE, Brendan M. KAYES, Isik C. KIZILYALLI
  • Patent number: 9716196
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: July 25, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
  • Patent number: 9691921
    Abstract: Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 27, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Harry Atwater, Brendan Kayes, Isik C. Kizilyalli, Hui Nie
  • Publication number: 20170133481
    Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
    Type: Application
    Filed: May 17, 2016
    Publication date: May 11, 2017
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Patent number: 9525039
    Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: December 20, 2016
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Hui Nie, Quentin Diduck, Ozgur Aktas
  • Patent number: 9508838
    Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: November 29, 2016
    Assignee: Avogy, Inc.
    Inventors: Linda Romano, Andrew Edwards, Dave P. Bour, Isik C. Kizilyalli
  • Patent number: 9502544
    Abstract: A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 22, 2016
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Linda Romano, David P. Bour
  • Patent number: 9484470
    Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 1, 2016
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Richard J. Brown, Donald R. Disney
  • Patent number: 9450112
    Abstract: A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: September 20, 2016
    Assignee: Avogy, Inc.
    Inventors: Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, Madhan Raj
  • Patent number: 9397186
    Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: July 19, 2016
    Assignee: Avogy, Inc.
    Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli
  • Publication number: 20160190351
    Abstract: A vertical field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
    Type: Application
    Filed: October 19, 2015
    Publication date: June 30, 2016
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
  • Publication number: 20160190296
    Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.
    Type: Application
    Filed: September 14, 2015
    Publication date: June 30, 2016
    Inventors: Linda Romano, Andrew P. Edwards, Richard J. Brown, David P. Bour, Hui Nie, Isik C. Kizilyalli, Thomas R. Prunty, Madhan M. Raj
  • Patent number: 9368582
    Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: June 14, 2016
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, David P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Patent number: 9330918
    Abstract: A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: May 3, 2016
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty