Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Abstract: An apparatus and a method of making are disclosed for an improved interposer comprises a wide bandgap semiconductor interposer such as silicon carbide (SiC) with a plurality of connectors formed in situ within the interposer for connecting the integrated circuit die to the substrate. The plurality of connectors may include carbon electrical connectors and/or optical wave guide connectors formed an angle within the interposer. The improved interposer may include a with the integrated circuit die disposed in the recess and thermally coupled to the silicon carbide (SiC) interposer for providing a heat sink for the integrated circuit die. A first and a second recess may be formed in separate surfaces of the silicon carbide (SiC) interposer enabling multiple interposers to be stacked upon one another.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: Microelectronic devices with an embedded die substrate on an interposer are described. For example, a microelectronic device includes a substrate housing an embedded die. At least one surface die is retained above a first outermost surface of the substrate. An interposer is retained proximate a second outermost surface of the substrate.

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.