Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for using projection patterning in making an electronic substrate with an embedded die. In one embodiment, a method may include providing a die embedded in dielectric material of a substrate, and projecting a laser beam through a mask with a preconfigured pattern to create a projected mask pattern on a surface of the dielectric material in accordance with the preconfigured pattern. The projected mask pattern may include a via disposed over the die. Other embodiments may be described and/or claimed.

Abstract: This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

Abstract: Embodiments of the present disclosure are directed towards package assembly configurations for multiple dies and associated techniques. In one embodiment, a package assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die mounted on the first side and electrically coupled with the package substrate by one or more first die-level interconnects, a second die mounted on the second side and electrically coupled with the package substrate by one or more second die-level interconnects and package-level interconnect structures disposed on the first side of the package substrate and configured to route electrical signals between the first die and an electrical device external to the package substrate and between the second die and the external device. Other embodiments may be described and/or claimed.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract: An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition.

Abstract: A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.

Abstract: This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: A first acousto-optic deflector receives a laser beam. The first acousto-optic deflector diffracts the received laser beam along a first axis. A second acousto-optic deflector receives the diffracted laser beam. The second acousto-optic deflector diffracts the received diffracted laser beam along a second axis.

Abstract: Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive circuitry can be removably coupled with a display device via an array of contact members. The display device can include image-producing elements or pixels that can be selectively driven by the backpanel device via corresponding portions of the array of contact members. Multiple display devices can be disposed adjacently on one or more backpanel devices such that an image displayed across the multiple display devices appears seamless.

Abstract: A method, electronic device and system for displaying background images on an electronic device, wherein the electronic device includes a face that has at least one edge and a display visible in the face. The display extends to at least one edge of the face. Furthermore, a processor is coupled to the display and a photosensor is coupled to the processor. The photosensor is configured to capture background images of a background obscured behind the device when viewing the device face. The processor is configured to composite the background image with a second image.

Abstract: This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract: Substrate cores for laser through hole formation are described. Substrate core embodiments include a plurality of reinforcement material layers and a microfiller loaded resin disposed between the plurality of reinforcement material layers. Microfiller and reinforcement materials are selected to reduce opto-thermal mismatch for a laser of a predetermined bandwidth. In embodiments, the reinforcement material may include a fibrous polymer, reducing the thermal contrast with the microfiller loaded resin, and/or include a chromophore that absorbs within the laser bandwidth. In further embodiments, the microfiller is of a material having a high melting temperature to reduce thermal contrast with the reinforcement material.

Abstract: Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.