Patents by Inventor Issei Yamamoto

Issei Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11944427
    Abstract: The learning system includes a data generation unit configured to generate learning data based on rehabilitation data and a learning unit configured to perform machine learning using the learning data. A sensor is provided to detect a plurality of motion amounts in a walking motion of a trainee, and it is evaluated that, when one of the motion amounts matches one of abnormal walking criteria, that the walking motion is an abnormal walking pattern that meets the matched abnormal walking criterion. The data generation unit generates each of the pieces of rehabilitation data before and after a change in the results of evaluation of the abnormal walking pattern as learning data. The learning unit sequentially inputs each of the pieces of rehabilitation data as one data set, thereby performing machine learning.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 2, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Nobuhisa Otsuki, Issei Nakashima, Manabu Yamamoto, Hodaka Kito
  • Patent number: 11937918
    Abstract: The learning apparatus includes a data generation unit configured to generate learning data based on rehabilitation data and a learning unit configured to perform machine learning using the learning data. A sensor is provided to detect a plurality of motion amounts in a walking motion of a trainee, and it is evaluated that, when one of the motion amounts matches one of abnormal walking criteria, that the walking motion is an abnormal walking pattern that meets the matched abnormal walking criterion. The data generation unit generates each of the pieces of rehabilitation data before and after a change in the results of evaluation of the abnormal walking pattern as learning data. The learning unit sequentially inputs each of the pieces of rehabilitation data as one data set, thereby performing machine learning.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 26, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Nobuhisa Otsuki, Issei Nakashima, Manabu Yamamoto, Hodaka Kito
  • Patent number: 11929173
    Abstract: The server is a learning apparatus including a data acquisition unit and a learning unit. The data acquisition unit acquires profile data and a selected assistance level as learning data. The profile data indicates a profile related to a trainee before executing rehabilitation regarding rehabilitation executed using a walking training apparatus as a rehabilitation support system. The selected assistance level is an assistance level selected at the time of executing the rehabilitation. The learning unit learns to determine a recommended assistance level recommended to be selected when the trainee uses the rehabilitation support system based on the learning data. Further, the learning unit generates a trained model that receives the profile data and outputs the recommended assistance level based on the learning.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 12, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Nobuhisa Otsuki, Ai Kurokawa, Issei Nakashima, Manabu Yamamoto, Taiga Matsumoto, Hiroaki Daba
  • Patent number: 11925458
    Abstract: A motion state monitoring system, a training support system, a motion state monitoring method, and a program capable of suitably managing measurement results according to an attaching direction of a sensor are provided. A motion state monitoring system according to the present disclosure monitors a motion state of a target part of a subject's body. The motion state monitoring system includes an acquisition unit, an attaching direction detection unit, and a control processing unit. The acquisition unit acquires sensing information of a sensor attached to the target part. The attaching direction detection unit detects an attaching direction of the sensor. The control processing unit outputs information related to the sensing information in association with the attaching direction.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: March 12, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Makoto Kobayashi, Toru Miyagawa, Issei Nakashima, Keisuke Suga, Masayuki Imaida, Manabu Yamamoto, Yohei Otaka, Masaki Katoh, Asuka Hirano, Taiki Yoshida
  • Patent number: 11923284
    Abstract: A wiring substrate that is provided enables stray capacitance between a first electrode and a second electrode to be prevented from varying when an undulation occurs in the wiring substrate. Insulating layers are stacked. A first electrode and a second electrode are formed between the same layers at an interval. The thickness of the first electrode is more than the thickness of the second electrode. The lower main surface of the first electrode is located at a position lower than the lower main surface of the second electrode, and the upper main surface of the first electrode is located at a position higher than the upper main surface of the second electrode when seen through in a direction perpendicular to a stacking direction of the insulating layers.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 5, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryota Asai, Issei Yamamoto
  • Publication number: 20230413439
    Abstract: Wiring board includes rigid board and flexible board laminated on rigid board. Cavity recessed in thickness direction of rigid board is formed in surface of rigid board which is located on flexible board side. Side surface and bottom surface of cavity are formed of rigid board. Top surface of cavity is formed of flexible board.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventor: Issei YAMAMOTO
  • Publication number: 20230371183
    Abstract: A wiring board includes at least one insulating layer, plurality of conductive members, at least one land electrode formed at position overlapping first surface in plan view of insulating layer as viewed from first surface side, land electrode being connected to each of at least one conductive member, and coil conductor provided inside insulating layer or on second surface on back side of first surface in insulating layer and having winding axis intersecting first surface. Plurality of conductive members includes first conductive member at position where at least part of the first conductive member overlaps opening of the coil conductor in plan view seen from first surface side, and second conductive member at position deviated from opening of coil conductor in plan view seen from first surface side. Area of first conductive member is smaller than area of second conductive member in plan view seen from first surface side.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Yoshiki TOBITA, Issei YAMAMOTO
  • Publication number: 20230371182
    Abstract: To provide wiring board capable of reducing influence of variation in size of conductive member on coil conductor. Wiring board according to present disclosure includes insulating layer, plurality of land electrodes formed on lower surface of insulating layer, solder ball formed on surface of at least one of plurality of land electrodes, and coil conductor provided inside insulating layer and having winding axis intersecting lower surface. Plurality of land electrodes includes electrode at a position overlapped opening of coil conductor in plan view seen at the wiring board from lower surface side, and second electrode at a position deviated from opening of coil conductor in plan view. Area of first electrode is larger than area of second electrode in plan view.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Yoshiki TOBITA, Issei YAMAMOTO
  • Patent number: 11659659
    Abstract: A ceramic electronic component of the present disclosure includes a component body including a ceramic layer, at least one terminal electrode provided on one main surface of the component body, and an insulating covering layer provided across the ceramic layer and the terminal electrode to cover part, instead of an entire circumference, of a peripheral edge portion of the terminal electrode, wherein when viewed in plan view from one main surface of the component body, the covering layer intersects with the terminal electrode at a non-perpendicular angle at an intersection of the covering layer and the terminal electrode not covered with the covering layer.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: May 23, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Naoya Murakita, Yoshihito Otsubo, Issei Yamamoto, Yuta Morimoto
  • Patent number: 11658405
    Abstract: An antenna-attached substrate according to the present disclosure includes a substrate layer, a lower antenna element that is disposed in the substrate layer, an antenna-holding layer that is stacked on an upper surface of the substrate layer, and an upper antenna element that is disposed in the antenna-holding layer and that faces an upper surface of the lower antenna element. The antenna-holding layer is composed of a dielectric material having a relative dielectric constant lower than that of the substrate layer. A lower surface, a side surface, and an upper surface of the upper antenna element are covered by the antenna-holding layer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 23, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Morimoto, Issei Yamamoto
  • Publication number: 20230113966
    Abstract: An electronic component including: an electronic component body; at least one electrode on a surface of the electronic component body; and a cover layer having insulating properties on at least a part of a periphery of the electrode and extending across a boundary between the periphery of the electrode and the surface of the electronic component body, wherein the electrode includes, on the at least part of the periphery, a lower electrode closer to the surface of the electronic component body and an upper electrode on the lower electrode, the lower electrode extends more outward than the upper electrode to create a step at the at least part of the periphery of the electrode, and at the step at the periphery of the electrode, the cover layer extends from a surface of the upper electrode to a portion with no electrodes on the surface of the electronic component body.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Toru YASO, Masahiro TERAMOTO, Naoya MURAKITA, Issei YAMAMOTO
  • Patent number: 11605873
    Abstract: A substrate with an antenna according to the present disclosure includes a circuit board having one main surface and the other main surface, and an antenna element mounted on the one main surface of the circuit board. When viewed from a thickness direction, an area of the one main surface of the circuit board is larger than an area of the other main surface, and the antenna element is mounted on at least a part of a region that is on the one main surface of the circuit board and that protrudes from the other main surface.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: March 14, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshitaka Echikawa, Issei Yamamoto, Ikuo Deguchi
  • Patent number: 11510311
    Abstract: An electronic component module (100) includes a module board (10) having electronic components (40) mounted on at least one of a first surface (front surface) (12) and a second surface (back surface) (14), mold portions (22 and 23), and a shield (32). The mold portions (22 and 23) cover the mounted electronic components (40). The shield (32) covers at least a part of the mold portions (22 and 23) and the side surfaces of the module board (10). Protrusions (15) protruding from the side surfaces are formed on the module board (10). The shield (32) is separated by the protrusions (15).
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: November 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Issei Yamamoto, Akio Katsube
  • Patent number: 11349449
    Abstract: Provided is a laminated electronic component in which defective formation is unlikely to cause in a shield conductor layer on a side surface of a laminate. The laminated electronic component includes a laminate 1, in which substrate layers 1a to 1i are laminated, having an outer surface including a first main surface 1B, a second main surface 1T, and a side surface 1S, internal electrodes (a ground electrode 2, coil electrodes 3, capacitor electrodes 4, and wiring electrodes 5), an external electrode 7, and a first plating layer 9 formed on a surface of the external electrode 7.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 31, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Issei Yamamoto, Atsunobu Okazaki, Yuki Asano
  • Patent number: 11322830
    Abstract: A substrate equipped with an antenna of the present disclosure includes a circuit substrate and an antenna element. When viewed from a thickness direction, an area of one principal surface of the circuit substrate is larger than that of another principal surface thereof, and each of the one principal surface and the other principal surface of the circuit substrate is formed in a rectangular shape. When a maximum width between a first outer periphery of the other principal surface projected onto the one principal surface and a first outer periphery of the one principal surface is defined as W1, the antenna element is mounted in at least part of a region on the one principal surface of the circuit substrate, in which the region has the width W1 from the second outer periphery of the other principal surface projected onto the one principal surface toward the inner side.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: May 3, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshitaka Echikawa, Issei Yamamoto, Ikuo Deguchi
  • Patent number: 11212906
    Abstract: A laminated substrate that includes a substrate body having a plurality of laminated ceramic layers containing a first glass; a wiring conductor within the substrate body and made from silver, copper, a silver alloy, or a copper alloy; and a thermal conductor within or on a main surface of the substrate body. The thermal conductor is at least one of (1) a thermal via penetrating a part of a first ceramic layer of the plurality of laminated ceramic layers in a thickness direction thereof, and (2) a heat spreader extending along a main surface of the first ceramic layer of the plurality of laminated ceramic layers. A first thermal conductivity of the thermal conductor is higher than a second thermal conductivity of the first ceramic layer, and the thermal conductor contains an insulating ceramic as a main material thereof, and further contains a second glass.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: December 28, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kosuke Sugiura, Issei Yamamoto
  • Patent number: 11196177
    Abstract: An antenna-mounted substrate includes a first patch antenna, a second patch antenna disposed to face one principal surface of the first patch antenna, and a ground electrode disposed to face the other principal surface of the first patch antenna, the antenna-mounted substrate further including an antenna holding layer holding the second patch antenna, an inter-antenna layer positioned between the first patch antenna and the second patch antenna, and a substrate layer positioned between the first patch antenna and the ground electrode, those three layers being positioned in the mentioned order, wherein the inter-antenna layer is made of a dielectric material, and a relation of ?r3>?r1??r2 is satisfied on an assumption that a relative permittivity of the antenna holding layer is denoted by ?r1, a relative permittivity of the inter-antenna layer is denoted by ?r2, and a relative permittivity of the substrate layer is denoted by ?r3.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: December 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Patent number: 11152157
    Abstract: Provided is a stacked electronic component having: a stacked body 1 in which ceramic layers 1a to 1h are stacked, the stacked body having an a upper surface U and side surfaces S; at least one recess portion 8 formed on the upper surface U that indicates at least one of a mark, a letter, or a number; electrodes 3, 4, 5, 6 formed between the layers of the stacked body 1; and a shield layer 9 formed on the upper surface U and the side surfaces S of the stacked body 1. Right below an inner bottom surface of the recess portion 8 of the stacked body 1, there is provided a no-electrode region NE in which the electrodes 3, 4, 5, 6 are not formed, the no-electrode region NE having a thickness which is equal to or larger than a depth of the recess portion 8.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: October 19, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Issei Yamamoto, Kunihiro Miyahara, Yoshihito Otsubo
  • Patent number: 11140778
    Abstract: A multilayer ceramic substrate according to the present disclosure has ceramic layers and a patterned conductor, and a cavity is formed in the multilayer ceramic substrate. The cavity reaches to any one of principal surfaces of the multilayer ceramic substrate and forms an opening, and the opening is covered with a sealing member at the principal surface of the multilayer ceramic substrate.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: October 5, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Patent number: 11121054
    Abstract: A module improves a heat-releasing effect and that can be stably mounted on a mother substrate or the like. The module includes: a first component mounted on one main surface of a wiring substrate and generates heat; second components mounted on the one main surface of the wiring substrate; a sealing resin layer that seals the first component and the second components so as not to cover a top surface of the first component; and heat-dissipating parts arranged on the top surface of the first component. The height of the highest positions of the heat-dissipating parts relative to the one main surface is less than or equal to the position of a highest surface out of a surface of the sealing resin layer that is on the opposite side from the surface of the sealing resin layer that faces the one main surface.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: September 14, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Issei Yamamoto, Tadashi Nomura