Patents by Inventor Issei Yamamoto

Issei Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200305272
    Abstract: A laminated substrate that includes a substrate body having a plurality of laminated ceramic layers containing a first glass; a wiring conductor within the substrate body and made from silver, copper, a silver alloy, or a copper alloy; and a thermal conductor within or on a main surface of the substrate body. The thermal conductor is at least one of (1) a thermal via penetrating a part of a first ceramic layer of the plurality of laminated ceramic layers in a thickness direction thereof, and (2) a heat spreader extending along a main surface of the first ceramic layer of the plurality of laminated ceramic layers. A first thermal conductivity of the thermal conductor is higher than a second thermal conductivity of the first ceramic layer, and the thermal conductor contains an insulating ceramic as a main material thereof, and further contains a second glass.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Kosuke Sugiura, Issei Yamamoto
  • Publication number: 20200303813
    Abstract: An antenna-attached substrate according to the present disclosure includes a substrate layer, a lower antenna element that is disposed in the substrate layer, an antenna-holding layer that is stacked on an upper surface of the substrate layer, and an upper antenna element that is disposed in the antenna-holding layer and that faces an upper surface of the lower antenna element. The antenna-holding layer is composed of a dielectric material having a relative dielectric constant lower than that of the substrate layer. A lower surface, a side surface, and an upper surface of the upper antenna element are covered by the antenna-holding layer.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Yuta MORIMOTO, Issei YAMAMOTO
  • Patent number: 10770223
    Abstract: The present disclosure is intended to reduce connection resistance between a shield film and a ground electrode, and to improve characteristics of the shield film. A high frequency component 1a includes a ceramic substrate 2, a ground electrode 3a disposed inside the ceramic substrate 2, a shield film 4 covering an upper surface 2a and lateral surfaces 2c of the ceramic substrate 2, and connecting portions 6a connecting the ground electrode 3a and the shield film 4, wherein the ground electrode 3a is formed using a conductive paste that contains a metal ingredient, powder, and a material constituting the ceramic substrate 2, and a weight rate of a metal ingredient in the connecting portions 6a is higher than that of the metal ingredient in the ground electrode 3a.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: September 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Patent number: 10772244
    Abstract: The characteristics of a shield wall that prevents the mutual interference of the noise between components are improved by lowering the resistance of the shield wall. A high-frequency module 1a includes a wiring board 2, a plurality of components 3a to 3e mounted on an upper surface 2a of the wiring board 2, a sealing resin layer 4 stacked on the upper surface 2a of the wiring board 2 to seal the components 3a to 3e, and a shield wall 5 disposed between the adjacent components in the sealing resin layer 4. A part of the shield wall 5 is constituted of metal pins 5a standing on the upper surface 2a of the wiring board 2.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: September 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Issei Yamamoto
  • Publication number: 20200266549
    Abstract: An antenna-mounted substrate includes a first patch antenna, a second patch antenna disposed to face one principal surface of the first patch antenna, and a ground electrode disposed to face the other principal surface of the first patch antenna, the antenna-mounted substrate further including an antenna holding layer holding the second patch antenna, an inter-antenna layer positioned between the first patch antenna and the second patch antenna, and a substrate layer positioned between the first patch antenna and the ground electrode, those three layers being positioned in the mentioned order, wherein the inter-antenna layer is made of a dielectric material, and a relation of ?r3>?r1??r2 is satisfied on an assumption that a relative permittivity of the antenna holding layer is denoted by ?r1, a relative permittivity of the inter-antenna layer is denoted by ?r2, and a relative permittivity of the substrate layer is denoted by ?r3.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventor: Issei YAMAMOTO
  • Patent number: 10660227
    Abstract: An electronic module includes a substrate having a first main surface and a second main surface, first electronic components on the first main surface, second electronic components on the second main surface, a first sealing resin portion, and a second sealing resin portion. Through holes are formed so as to extend through the substrate and the first sealing resin portion. A third electronic component is placed in the through holes. An area between the through holes and the third electronic component is filled with the second sealing resin portion, and the second sealing resin portion is formed to be exposed at a surface of the first sealing resin portion. When viewed in a direction perpendicular to the first main surface, the second sealing resin portion surrounds the third electronic component. The first sealing resin portion and the second sealing resin portion are made of different types of resins.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 19, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Patent number: 10600560
    Abstract: An electronic component includes a main body, an inner conductor inside the main body, one or more outer electrodes on a bottom surface of the main body and not provided on four side surfaces of the main body, and a shield electrode covering the four side surfaces of the main body and having a cylindrical or substantially cylindrical shape, the shield electrode not being physically connected to any of the one or more outer electrodes at a surface of the main body and being connected to the inner conductor at a surface of the main body.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: March 24, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka Masuda, Kunihiro Miyahara, Yosuke Matsushita, Issei Yamamoto
  • Publication number: 20200082990
    Abstract: Provided is a stacked electronic component having: a stacked body 1 in which ceramic layers 1a to 1h are stacked, the stacked body having an a upper surface U and side surfaces S; at least one recess portion 8 formed on the upper surface U that indicates at least one of a mark, a letter, or a number; electrodes 3, 4, 5, 6 formed between the layers of the stacked body 1; and a shield layer 9 formed on the upper surface U and the side surfaces S of the stacked body 1. Right below an inner bottom surface of the recess portion 8 of the stacked body 1, there is provided a no-electrode region NE in which the electrodes 3, 4, 5, 6 are not formed, the no-electrode region NE having a thickness which is equal to or larger than a depth of the recess portion 8.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Issei YAMAMOTO, Kunihiro MIYAHARA, Yoshihito OTSUBO
  • Patent number: 10546820
    Abstract: A radio frequency module includes a wiring substrate, a plurality of components mounted on an upper surface of the wiring substrate, a sealing resin layer laminated on the upper surface of the wiring substrate and covering the plurality of components, a groove formed in an upper surface of the sealing resin layer and extending between predetermined components of the plurality of components, and a shielding wall made of conductive paste in the groove. The sealing resin layer has a stepped area defining the higher portion and lower portion in the upper surface. The groove intersects the stepped area when the wiring substrate is seen in plan view.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihisa Masuda, Ryoichi Kita, Issei Yamamoto, Katsuki Nakanishi, Yukio Nakazawa
  • Publication number: 20200027825
    Abstract: A wiring substrate that is provided enables stray capacitance between a first electrode and a second electrode to be prevented from varying when an undulation occurs in the wiring substrate. Insulating layers are stacked. A first electrode and a second electrode are formed between the same layers at an interval. The thickness of the first electrode is more than the thickness of the second electrode. The lower main surface of the first electrode is located at a position lower than the lower main surface of the second electrode, and the upper main surface of the first electrode is located at a position higher than the upper main surface of the second electrode when seen through in a direction perpendicular to a stacking direction of the insulating layers.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Ryota ASAI, Issei YAMAMOTO
  • Publication number: 20190341329
    Abstract: A module improves a heat-releasing effect and that can be stably mounted on a mother substrate or the like. The module includes: a first component mounted on one main surface of a wiring substrate and generates heat; second components mounted on the one main surface of the wiring substrate; a sealing resin layer that seals the first component and the second components so as not to cover a top surface of the first component; and heat-dissipating parts arranged on the top surface of the first component. The height of the highest positions of the heat-dissipating parts relative to the one main surface is less than or equal to the position of a highest surface out of a surface of the sealing resin layer that is on the opposite side from the surface of the sealing resin layer that faces the one main surface.
    Type: Application
    Filed: July 11, 2019
    Publication date: November 7, 2019
    Inventors: Issei YAMAMOTO, Tadashi NOMURA
  • Patent number: 10455748
    Abstract: A high-frequency module includes a wiring board, a component that is mounted on an upper surface of the wiring board, a sealing resin layer that is laminated on the upper surface of the wiring board and that seals the component, a first shield layer that is laminated on the sealing resin layer so as to cover an opposite surface of the sealing resin layer and a peripheral side surface of the sealing resin layer, the opposite surface being opposite to the upper surface of the wiring board, and a second shield layer that is laminated on a portion of the first shield layer that covers the peripheral side surface of the sealing resin layer. In this case, even if the first shield layer cannot be made thick enough for obtaining desired shield characteristics, the second shield layer can provide a thickness corresponding to the insufficient thickness.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 22, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Issei Yamamoto
  • Publication number: 20190289737
    Abstract: An electronic module includes a substrate having a first main surface and a second main surface, first electronic components on the first main surface, second electronic components on the second main surface, a first sealing resin portion, and a second sealing resin portion. Through holes are formed so as to extend through the substrate and the first sealing resin portion. A third electronic component is placed in the through holes. An area between the through holes and the third electronic component is filled with the second sealing resin portion, and the second sealing resin portion is formed to be exposed at a surface of the first sealing resin portion. When viewed in a direction perpendicular to the first main surface, the second sealing resin portion surrounds the third electronic component. The first sealing resin portion and the second sealing resin portion are made of different types of resins.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventor: Issei YAMAMOTO
  • Patent number: 10349512
    Abstract: A high-frequency module includes: a multilayer wiring board; a plurality of components mounted on an upper surface of the multilayer wiring board; a sealing resin layer laminated on the upper surface of the multilayer wiring board and sealing the plurality of components; a shield wall disposed within the sealing resin layer and between the predetermined components; and a surface layer conductor disposed between the upper surface of the multilayer wiring board and the shield wall so as to overlap the shield wall in a plan view of the multilayer wiring board. The shield wall is formed in a polyline shape having bent portions in the plan view, and has, at the bent portions, projection portions penetrating the surface layer conductor.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Issei Yamamoto, Takuya Murayama, Tadashi Nomura
  • Publication number: 20190208622
    Abstract: A ceramic electronic component according to the present disclosure includes a ceramic insulator and conductor portions including inner conductors disposed inside the ceramic insulator and outer conductors disposed outside the ceramic insulator, wherein each conductor portion has a surface and a back surface opposite to the surface, and at least one of the conductor portions includes a flat portion in which the conductor thickness is constant, surface corner portions having a round-chamfered shape in the direction from the surface toward the back surface of the inner conductor or the outer conductor, and back surface corner portions having a round-chamfered shape in the direction from the back surface toward the surface of the inner conductor or the outer conductor.
    Type: Application
    Filed: February 1, 2019
    Publication date: July 4, 2019
    Inventors: Yosuke MATSUSHITA, Issei YAMAMOTO, Shigeru ENDO, Yoshihito OTSUBO
  • Publication number: 20190166690
    Abstract: A ceramic electronic component according to the present disclosure includes a wiring formation layer including a ceramic insulation layer containing a low-temperature co-fired ceramic material and a wiring pattern formed on the ceramic insulation layer. The wiring formation layer further has a plurality of dummy patterns formed on a portion of the ceramic insulation layer where the wiring pattern is not formed. The wiring width of the dummy patterns is less than the minimum value of the wiring width of the wiring pattern.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Issei YAMAMOTO, Yosuke MATSUSHITA
  • Patent number: 10256195
    Abstract: A module includes a wiring board, a plurality of components mounted on an upper surface of the wiring board, a sealing resin layer which seals the components provided on the upper surface of the wiring board, and a shield layer provided so as to cover a surface of the sealing resin layer. The shield layer includes an adhesion layer which is stacked on the surface of the sealing resin layer and includes a first adhesion film composed of a metal selected from the group consisting of Ti, Cr, Ni, TiCr, TiAl, NiAl, CrAl, and CrNiAl, a conductive layer which is stacked on the adhesion layer, and a protective layer which is stacked on the conductive layer and includes a protective film composed of a nitride, oxide, or oxynitride of a metal selected from the group consisting of Ti, Cr, Ni, TiCr, TiAl, NiAl, CrAl, and CrNiAl.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Issei Yamamoto, Atsushi Shimizu, Yoichi Takagi, Hideo Nakagoshi
  • Publication number: 20190051594
    Abstract: A module with high reliability is provided by inhibiting occurrences of air bubbles caused with rise in flow resistance of resin when a sealing resin layer is formed using a die. A module includes a wiring board, components mounted over an upper face of the wiring board, and a sealing resin layer laminated over the upper face. On the upper face, the sealing resin layer includes a high-level region with a long distance from the upper face of the wiring board, a low-level region with a short distance from the upper face, and a level difference region. In a portion included in the wiring board and corresponding to the low-level region and the level difference region, a thin portion is formed so as to be thinner than the remaining portion and overlaps the low-level region at least partially in a plan view.
    Type: Application
    Filed: October 5, 2018
    Publication date: February 14, 2019
    Inventor: Issei Yamamoto
  • Publication number: 20190043662
    Abstract: The present disclosure is intended to reduce connection resistance between a shield film and a ground electrode, and to improve characteristics of the shield film. A high frequency component 1a includes a ceramic substrate 2, a ground electrode 3a disposed inside the ceramic substrate 2, a shield film 4 covering an upper surface 2a and lateral surfaces 2c of the ceramic substrate 2, and connecting portions 6a connecting the ground electrode 3a and the shield film 4, wherein the ground electrode 3a is formed using a conductive paste that contains a metal ingredient, powder, and a material constituting the ceramic substrate 2, and a weight rate of a metal ingredient in the connecting portions 6a is higher than that of the metal ingredient in the ground electrode 3a.
    Type: Application
    Filed: October 10, 2018
    Publication date: February 7, 2019
    Inventor: Issei Yamamoto
  • Patent number: 10193333
    Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 29, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Jun Adachi, Jun Urakawa, Issei Yamamoto