Abstract: A socket, such as a Land Grid Array (LGA) socket, for forming electrical connections between a first surface having a first contact array and a second surface having a second contact array. The socket includes a plurality of compliant contacts, each contact inserted into one of a plurality of passages that extend through a plate. Each contact has a first contact surface for electrically engaging the first contact array, and a second contact surface for electrically engaging the second contact array. At least one of the contacts is a low current contact, and at least one of the contacts is a high current contact capable of passing more current than the low current contact.

Abstract: A chip package for reduced EMI. In one embodiment, a chip package includes a semiconductor chip mounted on a substrate. First and second horizontal conductors may be present within the substrate. The semiconductor chip is coupled to the first and second horizontal conductors by a first and second pluralities of vertical conductors, respectively. The silicon chip may receive power via the first horizontal conductor and the first plurality of vertical conductors. The first and second horizontal conductors are connected to external connectors by third and fourth pluralities of vertical conductors, respectively. One or more capacitors may be electrically coupled between the first and second horizontal conductors.

Abstract: A chip package for reduced EMI. In one embodiment, a chip package includes a semiconductor chip mounted on a substrate. First and second horizontal conductors may be present within the substrate. The semiconductor chip is coupled to the first and second horizontal conductors by a first and second pluralities of vertical conductors, respectively. The silicon chip may receive power via the first horizontal conductor and the first plurality of vertical conductors. The first and second horizontal conductors are connected to external connectors by third and fourth pluralities of vertical conductors, respectively. One or more capacitors may be electrically coupled between the first and second horizontal conductors.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.

Abstract: A method for constructing a capacitor having an increased equivalent series resistance (ESR) is disclosed. In one embodiment, a capacitor includes a plurality of capacitor plates comprised of a conductive material and first and second capacitor terminals. At least one of the capacitor plates is coupled to the first terminal and at least one of the capacitor plates is coupled to the second terminal. At least one of the plurality of capacitor plates includes a pattern, wherein the pattern is void of conductive material. The void in the conductive material formed by the pattern may cause a path of current flow through the capacitor plate to be substantially altered in comparison to a capacitor plate that is continuous. By using capacitor plates having voids of conductive material that cause the current path to be altered in comparison to continuous capacitor plates, a capacitor can be constructed having a higher ESR.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The PCB may include a signal layer for conveying signals to and from the integrated circuit, but does not include any means for providing core power to the integrated circuit. Thus, all core power provided to the integrated circuit may be supplied by the power laminate.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: Several methods are presented for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors between the planar conductors. The methods include bypass capacitor selection criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, and n discrete electrical capacitors electrically coupled between the planar conductors, where n≧2. The n capacitors have substantially the same capacitance C, mounted resistance Rm, and mounted inductance Lm. The electrical power distribution structure achieves an electrical impedance Z at a mounted resonant frequency fm-res of the capacitors. The mounted resistance Rm of each of the n capacitors is substantially equal to (n·Z). The mounted inductance Lm of each of the n capacitors is less than or equal to (0.

Abstract: A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: A method of direct plane attachment of capacitors is disclosed. In one embodiment, a printed circuit board (PCB) having a signal layer, a first conductive plane, and a second conductive plane is provided. The signal layer may be the outermost layer of the PCB, while the first conductive layer may be arranged between the signal layer and the second conductive layer. A cavity may be formed in the printed circuit board, wherein the cavity extends from the signal layer down to the first conductive plane. The cavity may be large enough to accommodate one or more capacitors. A first terminal of the capacitor may be attached to the first conductive plane. The second terminal of the capacitor may be mounted within an opening in the first conductive plane. The method may allow a bypass capacitor to be directly coupled to a power or reference plane.

Abstract: A method for determining the bypass capacitors in order to achieve a target impedance over a wide frequency range. In one embodiment, a power distribution system of an electronic circuit includes at least one pair of planar conductors, including a power plane and a ground plane. A first capacitor bank may be defined to provide bypassing in a frequency range extending from a maximum frequency down to a first frequency (also referred to as a deviation frequency). The electrical characteristics, or parameters of the first capacitor bank may include a first capacitance, a first resistance, and a first inductance (C10, R10, and L10, respectively). The first resistance may be set to be less than or equal to the required target impedance for the frequency range covered by the first capacitor bank.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Abstract: The problems outlined above may in large part be solved by a system and method for testing integrated passive components in a printed circuit board. In one embodiment, testing of integrated passive components may be conducted prior to completing the final lamination of the printed circuit board. The testing may be conducted on a tester having movable test probes. The method may include connecting a first test probe to a conductive plane, which may be electrically connected to the first terminals of two or more components. The conductive plane may be a ground plane, a power plane, or a signal plane. The first test probe may remain in a fixed position throughout the testing. A second test probe may be electrically connected to the second terminal of the first component. Following the connection of the second test probe, an electrical characteristic of the first component may be measured.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: A method for determining the bypass capacitors in order to achieve a target impedance over a wide frequency range. In one embodiment, a power distribution system of an electronic circuit includes at least one pair of planar conductors, including a power plane and a ground plane. A first capacitor bank may be defined to provide bypassing in a frequency range extending from a maximum frequency down to a first frequency (also referred to as a deviation frequency). The electrical characteristics, or parameters of the first capacitor bank may include a first capacitance, a first resistance, and a first inductance (C10, R10, and L10, respectively). The first resistance may be set to be less than or equal to the required target impedance for the frequency range covered by the first capacitor bank.