Patents by Inventor Istvan Novak

Istvan Novak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020163327
    Abstract: The problems outlined above may in large part be solved by a system and method for testing integrated passive components in a printed circuit board. In one embodiment, testing of integrated passive components may be conducted prior to completing the final lamination of the printed circuit board. The testing may be conducted on a tester having movable test probes. The method may include connecting a first test probe to a conductive plane, which may be electrically connected to the first terminals of two or more components. The conductive plane may be a ground plane, a power plane, or a signal plane. The first test probe may remain in a fixed position throughout the testing. A second test probe may be electrically connected to the second terminal of the first component. Following the connection of the second test probe, an electrical characteristic of the first component may be measured.
    Type: Application
    Filed: May 1, 2001
    Publication date: November 7, 2002
    Inventors: Istvan Novak, Valerie A. St. Cyr
  • Publication number: 20020145839
    Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.
    Type: Application
    Filed: March 16, 2001
    Publication date: October 10, 2002
    Inventors: Larry D. Smith, Istvan Novak, Michael C. Freda
  • Publication number: 20020129974
    Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The PCB may include a signal layer for conveying signals to and from the integrated circuit, but does not include any means for providing core power to the integrated circuit. Thus, all core power provided to the integrated circuit may be supplied by the power laminate.
    Type: Application
    Filed: March 16, 2001
    Publication date: September 19, 2002
    Inventors: Larry D. Smith, Istvan Novak, Michael C. Freda, Ali Hassanzadeh
  • Patent number: 6441313
    Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer. The pair of parallel planar conductors includes a first power supply plane suitable for use, for example, as a ground plane and a second power supply plane suitable for use, for example, as a power plane (e.g., VCC). The dielectric layer has a loss tangent value of at least 0.2, and preferably of at least 0.3. In one embodiment, the dielectric material between the power planes could have a frequency dependent loss tangent, such that a loss tangent value of 0.3 is achieved at and above the lowest resonance frequency of the planes.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: Istvan Novak
  • Patent number: 6215373
    Abstract: A system and method are presented for stabilizing the electrical impedance of a structure (e.g., an electrical interconnecting apparatus) including a pair of parallel planar conductors separated by a dielectric layer. The structure may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate. An electrical resistance connected between the planar conductors about a periphery of the structure serves to stabilize the electrical impedance of the structure, thereby reducing an amount of electromagnetic energy radiated from the structure. The electrical resistance may be multiple discrete electrical resistances dispersed about the periphery of the structure, and the structure need not be rectangular. For example, a portion of the periphery of the structure may define a curve. A general method for stabilizing the electrical impedance of the structure includes selecting a spacing distance.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: April 10, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Istvan Novak, Wai-Yeung Yip
  • Patent number: 6215372
    Abstract: Electrical resonances are reduced and noise propagation is attenuated in a multi-layer construction using planar power and ground planar conductors separated by insulating material by loading the power and ground planar conductors with a sufficient amount of capacitance, or series capacitance and resistance, at specific locations so that the planar conductors are electrically broken up into smaller sections which resonate at frequencies above the signal bandwidth. The propagation of injected noise is suppressed by the low-pass filter effect of the capacitive loading at the discrete locations. In accordance with one embodiment of the invention, islands of material with a dielectric constant higher than the dielectric constant of the overall insulator are placed at regular intervals where the capacitance of each high dielectric constant island is comparable to, or higher than, the capacitance of the “low” dielectric material which comprises the remainder of the insulating material.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: April 10, 2001
    Assignee: Sun Microsystems, Inc.
    Inventor: Istvan Novak
  • Patent number: 6104258
    Abstract: A system and method are presented for stabilizing the electrical impedance of an electrical interconnecting apparatus including a pair of parallel planar conductors separated by a dielectric layer. The electrical interconnecting apparatus may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate. The present method includes determining a characteristic impedance of the structure. An electrical resistance is electrically coupled between regions of the planar conductors near peripheries, wherein the electrical resistance has a value dependent upon the characteristic impedance of the structure. The electrical resistance may be a set of discrete electrical resistances (e.g., resistors) dispersed about regions near peripheries of the planar conductors, or a continuous "stripe" of electrical resistance between the regions.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: August 15, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: Istvan Novak